diff --git a/src/Kconfig b/src/Kconfig
index 91a3b29f63..94b3508ae4 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -338,10 +338,10 @@ source "src/mainboard/Kconfig"
 
 config CBFS_SIZE
 	hex "Size of CBFS filesystem in ROM"
-	default 0x100000 if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_SANDYBRIDGE || \
+	default 0x100000 if HAVE_INTEL_FIRMWARE || \
+	  NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_SANDYBRIDGE || \
 	  NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE || \
-	  NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE || NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE || \
-	  NORTHBRIDGE_INTEL_FSP_IVYBRIDGE || NORTHBRIDGE_INTEL_HASWELL || \
+	  NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE || \
 	  NORTHBRIDGE_INTEL_NEHALEM || SOC_INTEL_BAYTRAIL || SOC_INTEL_BRASWELL || \
 	  SOC_INTEL_BROADWELL
 	default 0x200000 if SOC_INTEL_FSP_BAYTRAIL
@@ -378,7 +378,9 @@ source "src/ec/acpi/Kconfig"
 source "src/ec/*/*/Kconfig"
 source "src/drivers/intel/fsp1_0/Kconfig"
 
+source "src/southbridge/intel/common/firmware/Kconfig"
 source "src/vendorcode/*/Kconfig"
+
 source "src/arch/*/Kconfig"
 
 endmenu
diff --git a/src/mainboard/intel/mohonpeak/Kconfig b/src/mainboard/intel/mohonpeak/Kconfig
index 2aaa766954..c16aad30fd 100644
--- a/src/mainboard/intel/mohonpeak/Kconfig
+++ b/src/mainboard/intel/mohonpeak/Kconfig
@@ -36,14 +36,6 @@ config MAINBOARD_DIR
 	string
 	default intel/mohonpeak
 
-config INCLUDE_ME
-	bool
-	default n
-
-config LOCK_MANAGEMENT_ENGINE
-	bool
-	default n
-
 config MAINBOARD_PART_NUMBER
 	string
 	default "Mohon Peak CRB"
diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig
new file mode 100644
index 0000000000..1f4d935f7c
--- /dev/null
+++ b/src/southbridge/intel/common/firmware/Kconfig
@@ -0,0 +1,94 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Google Inc.
+## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+
+config HAVE_INTEL_FIRMWARE
+	bool
+	help
+	  Chipset uses the Intel Firmware Descriptor to describe the
+	  layout of the SPI ROM chip.
+
+if HAVE_INTEL_FIRMWARE
+
+comment "Intel Firmware"
+
+config HAVE_IFD_BIN
+	bool "Add Intel descriptor.bin file"
+	help
+	  The descriptor binary
+
+config IFD_BIN_PATH
+	string "Path and filename of the descriptor.bin file"
+	depends on HAVE_IFD_BIN && !BUILD_WITH_FAKE_IFD
+
+config HAVE_ME_BIN
+	bool "Add Intel Management Engine firmware"
+	depends on USES_INTEL_ME && HAVE_IFD_BIN
+	help
+	  The Intel processor in the selected system requires a special firmware
+	  for an integrated controller called Management Engine (ME). The ME
+	  firmware might be provided in coreboot's 3rdparty/blobs repository. If
+	  not and if you don't have the firmware elsewhere, you can still
+	  build coreboot without it. In this case however, you'll have to make
+	  sure that you don't overwrite your ME firmware on your flash ROM.
+
+config ME_BIN_PATH
+	string "Path to management engine firmware"
+	depends on HAVE_ME_BIN
+
+##### Fake IFD #####
+
+config BUILD_WITH_FAKE_IFD
+	bool "Build with a fake IFD" if !HAVE_IFD_BIN
+	help
+	  If you don't have an Intel Firmware Descriptor (descriptor.bin) for your
+	  board, you can select this option and coreboot will build without it.
+	  The resulting coreboot.rom will not contain all parts required
+	  to get coreboot running on your board. You can however write only the
+	  BIOS section to your board's flash ROM and keep the other sections
+	  untouched. Unfortunately the current version of flashrom doesn't
+	  support this yet. But there is a patch pending [1].
+
+	  WARNING: Never write a complete coreboot.rom to your flash ROM if it
+	           was built with a fake IFD. It just won't work.
+
+	  [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
+
+config IFD_BIOS_SECTION
+	depends on BUILD_WITH_FAKE_IFD
+	string
+	default ""
+
+config IFD_ME_SECTION
+	depends on BUILD_WITH_FAKE_IFD
+	string
+	default ""
+
+config IFD_GBE_SECTION
+	depends on BUILD_WITH_FAKE_IFD
+	string
+	default ""
+
+config IFD_PLATFORM_SECTION
+	depends on BUILD_WITH_FAKE_IFD
+	string
+	default ""
+
+
+endif #INTEL_FIRMWARE
diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc
new file mode 100644
index 0000000000..7a97e37529
--- /dev/null
+++ b/src/southbridge/intel/common/firmware/Makefile.inc
@@ -0,0 +1,73 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Google Inc.
+## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+
+ifeq ($(CONFIG_HAVE_INTEL_FIRMWARE),y)
+
+# Run intermediate steps when producing coreboot.rom
+# that adds additional components to the final firmware
+# image outside of CBFS
+
+ifeq ($(CONFIG_HAVE_IFD_BIN),y)
+INTERMEDIATE+=add_intel_firmware
+endif
+
+ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
+INTERMEDIATE+=add_intel_firmware
+IFD_BIN_PATH := $(objgenerated)/ifdfake.bin
+IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \
+		$(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \
+		$(addprefix -g ,$(CONFIG_IFD_GBE_SECTION:"%"=%)) \
+		$(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%))
+else
+IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH)
+endif
+
+add_intel_firmware: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE)
+ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
+	printf "\n** WARNING **\n"
+	printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n"
+	printf "Never write a complete coreboot.rom with a fake IFD to your board's\n"
+	printf "flash ROM! Make sure that you only write valid flash regions.\n\n"
+	printf "    IFDFAKE    Building a fake Intel Firmware Descriptor\n"
+	$(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH)
+endif
+	printf "    DD         Adding Intel Firmware Descriptor\n"
+	dd if=$(IFD_BIN_PATH) \
+		of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
+ifeq ($(CONFIG_HAVE_ME_BIN),y)
+	printf "    IFDTOOL    me.bin -> coreboot.pre\n"
+	$(objutil)/ifdtool/ifdtool \
+		-i ME:$(CONFIG_ME_BIN_PATH) \
+		$(obj)/coreboot.pre
+	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
+endif
+ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y)
+	printf "    IFDTOOL    Locking Management Engine\n"
+	$(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre
+	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
+else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
+	printf "    IFDTOOL    Unlocking Management Engine\n"
+	$(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre
+	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
+endif
+
+PHONY+=add_intel_firmware
+
+endif
diff --git a/src/southbridge/intel/fsp_bd82x6x/Kconfig b/src/southbridge/intel/fsp_bd82x6x/Kconfig
index f60cbb1e64..fc2b6b36a2 100644
--- a/src/southbridge/intel/fsp_bd82x6x/Kconfig
+++ b/src/southbridge/intel/fsp_bd82x6x/Kconfig
@@ -33,6 +33,8 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	select PCIEXP_COMMON_CLOCK
 	select SPI_FLASH
 	select COMMON_FADT
+	select HAVE_INTEL_FIRMWARE
+	select USES_INTEL_ME
 
 config EHCI_BAR
 	hex
@@ -53,35 +55,4 @@ config HPET_MIN_TICKS
 	hex
 	default 0x80
 
-if HAVE_FSP_BIN
-
-config INCLUDE_ME
-	bool
-	default n
-	help
-	  Include the me.bin and descriptor.bin for Intel PCH.
-	  This is usually required for the PCH.
-
-config ME_PATH
-	string
-	depends on INCLUDE_ME
-	help
-	  The path of the ME and Descriptor files.
-
-config LOCK_MANAGEMENT_ENGINE
-	bool "Lock Management Engine section"
-	default n
-	depends on INCLUDE_ME
-	help
-	  The Intel Management Engine supports preventing write accesses
-	  from the host to the Management Engine section in the firmware
-	  descriptor. If the ME section is locked, it can only be overwritten
-	  with an external SPI flash programmer. You will want this if you
-	  want to increase security of your ROM image once you are sure
-	  that the ME firmware is no longer going to change.
-
-	  If unsure, say N.
-
-endif # HAVE_FSP_BIN
-
 endif
diff --git a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc
index 44144a0302..d96e641670 100644
--- a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc
+++ b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc
@@ -20,12 +20,7 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X),y)
 
-# Run an intermediate step when producing coreboot.rom
-# that adds additional components to the final firmware
-# image outside of CBFS
-ifeq ($(CONFIG_INCLUDE_ME),y)
-INTERMEDIATE+=bd82x6x_add_me
-endif
+subdirs-y += ../common/firmware
 
 ramstage-y += pch.c
 ramstage-y += azalia.c
@@ -51,27 +46,6 @@ smm-$(CONFIG_USBDEBUG) += usb_debug.c
 romstage-y += reset.c
 romstage-y += early_spi.c
 
-bd82x6x_add_me: $(obj)/coreboot.pre $(IFDTOOL)
-	printf "    DD         Adding Intel Firmware Descriptor\n"
-	dd if=$(call strip_quotes,$(CONFIG_ME_PATH))/descriptor.bin \
-		of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
-	printf "    IFDTOOL    me.bin -> coreboot.pre\n"
-	$(objutil)/ifdtool/ifdtool \
-		-i ME:$(call strip_quotes,$(CONFIG_ME_PATH))/me.bin \
-		$(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y)
-	printf "    IFDTOOL    Locking Management Engine\n"
-	$(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-else
-	printf "    IFDTOOL    Unlocking Management Engine\n"
-	$(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-endif
-
-PHONY += bd82x6x_add_me
-
 CPPFLAGS_common += -I$(src)/southbridge/intel/fsp_bd82x6x
 
 endif
diff --git a/src/southbridge/intel/fsp_rangeley/Kconfig b/src/southbridge/intel/fsp_rangeley/Kconfig
index 71782be04a..2c8ceacd9a 100644
--- a/src/southbridge/intel/fsp_rangeley/Kconfig
+++ b/src/southbridge/intel/fsp_rangeley/Kconfig
@@ -32,6 +32,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	select PCIEXP_ASPM
 	select PCIEXP_COMMON_CLOCK
 	select SPI_FLASH
+	select HAVE_INTEL_FIRMWARE
 
 config EHCI_BAR
 	hex
@@ -52,21 +53,11 @@ config HPET_MIN_TICKS
 	hex
 	default 0x80
 
-if HAVE_FSP_BIN
-
-config INCLUDE_ME
-	bool "Add Intel descriptor.bin file"
-	default n
-	help
-	  Include the descriptor.bin for rangeley.
-
-config ME_PATH
-	string "Path to descriptor.bin file"
-	depends on INCLUDE_ME
+config IFD_BIN_PATH
+	string
+	depends on HAVE_IFD_BIN
 	default "../intel/mainboard/intel/rangeley"
 	help
-	  The path of the descriptor.bin file.
-
-endif # HAVE_FSP_BIN
+	  The path and filename to the descriptor.bin file.
 
 endif
diff --git a/src/southbridge/intel/fsp_rangeley/Makefile.inc b/src/southbridge/intel/fsp_rangeley/Makefile.inc
index 0f9f59cdb5..1d35b54dc1 100644
--- a/src/southbridge/intel/fsp_rangeley/Makefile.inc
+++ b/src/southbridge/intel/fsp_rangeley/Makefile.inc
@@ -20,9 +20,7 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY),y)
 
-# Run an intermediate step when producing coreboot.rom
-# that adds additional components to the final firmware
-# image outside of CBFS
+subdirs-y += ../common/firmware
 
 ramstage-y += soc.c
 ramstage-y += lpc.c
@@ -39,16 +37,4 @@ romstage-y += romstage.c
 romstage-$(CONFIG_USBDEBUG) += usb_debug.c
 ramstage-$(CONFIG_USBDEBUG) += usb_debug.c
 
-
-ifeq ($(CONFIG_INCLUDE_ME),y)
-INTERMEDIATE+=rangeley_add_descriptor
-
-rangeley_add_descriptor: $(obj)/coreboot.pre $(IFDTOOL)
-	printf "    DD         Adding Intel Firmware Descriptor\n"
-	dd if=$(call strip_quotes,$(CONFIG_ME_PATH))/descriptor.bin \
-		of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
-endif
-
-PHONY += rangeley_add_descriptor
-
 endif
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index 2747b21cf9..2c71ab2a53 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -32,6 +32,8 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	select PCIEXP_ASPM
 	select PCIEXP_COMMON_CLOCK
 	select SPI_FLASH
+	select HAVE_INTEL_FIRMWARE
+	select USES_INTEL_ME
 
 config INTEL_LYNXPOINT_LP
 	bool
@@ -59,60 +61,20 @@ config HAVE_IFD_BIN
 	default y
 
 config BUILD_WITH_FAKE_IFD
-	bool "Build with a fake IFD"
+	bool
 	default y if !HAVE_IFD_BIN
-	help
-	  If you don't have an Intel Firmware Descriptor (ifd.bin) for your
-	  board, you can select this option and coreboot will build without it.
-	  Though, the resulting coreboot.rom will not contain all parts required
-	  to get coreboot running on your board. You can however write only the
-	  BIOS section to your board's flash ROM and keep the other sections
-	  untouched. Unfortunately the current version of flashrom doesn't
-	  support this yet. But there is a patch pending [1].
-
-	  WARNING: Never write a complete coreboot.rom to your flash ROM if it
-	           was built with a fake IFD. It just won't work.
-
-	  [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
-
-config IFD_BIOS_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
-
-config IFD_ME_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
-
-config IFD_GBE_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
-
-config IFD_PLATFORM_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
 
 config IFD_BIN_PATH
-	string "Path to intel firmware descriptor"
+	string
 	depends on !BUILD_WITH_FAKE_IFD
 	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
 
 config HAVE_ME_BIN
-	bool "Add Intel Management Engine firmware"
+	bool
 	default y
-	help
-	  The Intel processor in the selected system requires a special firmware
-	  for an integrated controller called Management Engine (ME). The ME
-	  firmware might be provided in coreboot's 3rdparty/blobs repository. If
-	  not and if you don't have the firmware elsewhere, you can still
-	  build coreboot without it. In this case however, you'll have to make
-	  sure that you don't overwrite your ME firmware on your flash ROM.
 
 config ME_BIN_PATH
-	string "Path to management engine firmware"
+	string
 	depends on HAVE_ME_BIN
 	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
 
@@ -133,16 +95,7 @@ config FINALIZE_USB_ROUTE_XHCI
 	  to the XHCI controller during the finalize SMM callback.
 
 config LOCK_MANAGEMENT_ENGINE
-	bool "Lock Management Engine section"
+	bool
 	default n
-	help
-	  The Intel Management Engine supports preventing write accesses
-	  from the host to the Management Engine section in the firmware
-	  descriptor. If the ME section is locked, it can only be overwritten
-	  with an external SPI flash programmer. You will want this if you
-	  want to increase security of your ROM image once you are sure
-	  that the ME firmware is no longer going to change.
-
-	  If unsure, say N.
 
 endif
diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
index a22251afc0..a42fe3946f 100644
--- a/src/southbridge/intel/lynxpoint/Makefile.inc
+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
@@ -19,10 +19,7 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y)
 
-# Run an intermediate step when producing coreboot.rom
-# that adds additional components to the final firmware
-# image outside of CBFS
-INTERMEDIATE:=lynxpoint_add_me
+subdirs-y += ../common/firmware
 
 ramstage-y += pch.c
 ramstage-y += azalia.c
@@ -66,45 +63,4 @@ ramstage-y += gpio.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += gpio.c
 endif
 
-ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
-IFD_BIN_PATH := $(objgenerated)/ifdfake.bin
-IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \
-		$(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \
-		$(addprefix -g ,$(CONFIG_IFD_GBE_SECTION:"%"=%)) \
-		$(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%))
-else
-IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH)
-endif
-
-lynxpoint_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE)
-ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
-	printf "\n** WARNING **\n"
-	printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n"
-	printf "Never write a complete coreboot.rom with a fake IFD to your board's\n"
-	printf "flash ROM! Make sure that you only write valid flash regions.\n\n"
-	printf "    IFDFAKE    Building a fake Intel Firmware Descriptor\n"
-	$(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH)
-endif
-	printf "    DD         Adding Intel Firmware Descriptor\n"
-	dd if=$(IFD_BIN_PATH) \
-		of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
-ifeq ($(CONFIG_HAVE_ME_BIN),y)
-	printf "    IFDTOOL    me.bin -> coreboot.pre\n"
-	$(objutil)/ifdtool/ifdtool \
-		-i ME:$(CONFIG_ME_BIN_PATH) \
-		$(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-endif
-ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y)
-	printf "    IFDTOOL    Locking Management Engine\n"
-	$(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
-	printf "    IFDTOOL    Unlocking Management Engine\n"
-	$(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-endif
-
-PHONY += lynxpoint_add_me
-
 endif