southbrige/intel/bd82x6x: add XHCI overcurrent map config

Change-Id: I9a40e5a1028c7674e6dd54742e6646ba48ce7696
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/9449
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Nicolas Reinecke 2015-04-16 23:25:00 +02:00 committed by Edward O'Callaghan
parent f21b657f27
commit 59aef5c79e
3 changed files with 6 additions and 0 deletions

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@ -94,6 +94,8 @@ struct southbridge_intel_bd82x6x_config {
uint32_t xhci_switchable_ports;
/* Ports which support SuperSpeed (USB 3.0 additional lanes). */
uint32_t superspeed_capable_ports;
/* Overcurrent Mapping for USB 3.0 Ports */
uint32_t xhci_overcurrent_mapping;
};
#endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */

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@ -449,6 +449,7 @@ early_usb_init (const struct southbridge_usb_port *portmap);
#define USBOCM2 0x35a4 /* 32bit */
/* XHCI USB 3.0 */
#define XOCM 0xc0 /* 32bit */
#define XUSB2PRM 0xd4 /* 32bit */
#define USB3PRM 0xdc /* 32bit */

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@ -33,6 +33,9 @@ static void usb_xhci_init(struct device *dev)
printk(BIOS_DEBUG, "XHCI: Setting up controller.. ");
if (config->xhci_overcurrent_mapping)
pci_write_config32(dev, XOCM, config->xhci_overcurrent_mapping);
/* lock overcurrent map */
reg32 = pci_read_config32(dev, 0x44);
reg32 |= 1;