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White space and typo fixes. This makes it easier to compare the s2895 & s2892. 

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4773 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson 2009-10-14 03:09:26 +00:00
parent cb69cb3e69
commit 59b2dc2cf2
6 changed files with 512 additions and 547 deletions
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2
src/cpu/amd/car/cache_as_ram.inc
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@ -250,7 +250,6 @@ clear_fixed_var_mtrr_out:
wrmsr wrmsr
#endif /* CONFIG_USE_FAILOVER_IMAGE == 1*/ #endif /* CONFIG_USE_FAILOVER_IMAGE == 1*/
#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 0)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 0)) #if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 0)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 0))
/* disable cache */ /* disable cache */
movl %cr0, %eax movl %cr0, %eax
@ -300,7 +299,6 @@ wbcache_post_fam10_setup:
andl $0x9fffffff, %eax andl $0x9fffffff, %eax
movl %eax, %cr0 movl %eax, %cr0
jmp_if_k8(fam10_end_part1) jmp_if_k8(fam10_end_part1)
/* So we need to check if it is BSP */ /* So we need to check if it is BSP */

42
src/mainboard/tyan/s2892/cache_as_ram_auto.c
View File

@ -1,6 +1,12 @@
#define ASSEMBLY 1 #define ASSEMBLY 1
#define __ROMCC__ #define __ROMCC__
#define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#include <stdint.h> #include <stdint.h>
#include <string.h> #include <string.h>
#include <device/pci_def.h> #include <device/pci_def.h>
@ -10,6 +16,8 @@
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include "option_table.h" #include "option_table.h"
#include "pc80/mc146818rtc_early.c" #include "pc80/mc146818rtc_early.c"
#define post_code(x) outb(x, 0x80)
#include "pc80/serial.c" #include "pc80/serial.c"
#include "arch/i386/lib/console.c" #include "arch/i386/lib/console.c"
#include "lib/ramtest.c" #include "lib/ramtest.c"
@ -34,10 +42,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void memreset_setup(void)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl) static void memreset(int controllers, const struct mem_controller *ctrl)
{ {
} }
@ -52,8 +56,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address); return smbus_read_byte(device, address);
} }
#define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c" #include "lib/generic_sdram.c"
@ -61,9 +63,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
/* tyan does not want the default */ /* tyan does not want the default */
#include "resourcemap.c" #include "resourcemap.c"
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/dualcore/dualcore.c"
#define CK804_NUM 1 #define CK804_NUM 1
@ -178,7 +177,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
unsigned nodes; unsigned nodes;
if (bist == 0) { if (bist == 0) {
init_cpus(cpu_init_detectedx); bsp_apicid = init_cpus(cpu_init_detectedx);
} }
// post_code(0x32); // post_code(0x32);
@ -190,11 +189,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */ /* Halt if there was a built in self test failure */
report_bist_failure(bist); report_bist_failure(bist);
setup_s2892_resource_map(); setup_mb_resource_map();
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
needs_reset = setup_coherent_ht_domain(); needs_reset = setup_coherent_ht_domain();
@ -210,7 +205,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ck804_early_setup_x(); needs_reset |= ck804_early_setup_x();
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); printk_info("ht reset -\n");
soft_reset(); soft_reset();
} }
@ -221,23 +216,8 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
fill_mem_ctrl(nodes, ctrl, spd_addr); fill_mem_ctrl(nodes, ctrl, spd_addr);
enable_smbus(); enable_smbus();
#if 0
dump_spd_registers(&cpu[0]);
#endif
#if 0
dump_smbus_registers();
#endif
memreset_setup();
sdram_initialize(nodes, ctrl); sdram_initialize(nodes, ctrl);
#if 0
print_pci_devices();
#endif
#if 0
dump_pci_devices();
#endif
post_cache_as_ram(); post_cache_as_ram();
} }

5
src/mainboard/tyan/s2892/resourcemap.c
View File

@ -3,7 +3,7 @@
* *
*/ */
static void setup_s2892_resource_map(void) static void setup_mb_resource_map(void)
{ {
static const unsigned int register_values[] = { static const unsigned int register_values[] = {
/* Careful set limit registers before base registers which contain the enables */ /* Careful set limit registers before base registers which contain the enables */
@ -256,11 +256,8 @@ static void setup_s2892_resource_map(void)
// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */ // PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
}; };
int max; int max;
max = ARRAY_SIZE(register_values); max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max); setup_resource_map(register_values, max);
} }

8
src/mainboard/tyan/s2895/cache_as_ram_auto.c
View File

@ -4,7 +4,6 @@
#define K8_ALLOCATE_IO_RANGE 1 #define K8_ALLOCATE_IO_RANGE 1
//#define K8_SCAN_PCI_BUS 1 //#define K8_SCAN_PCI_BUS 1
//used by raminit
#define QRANK_DIMM_SUPPORT 1 #define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS==1 #if CONFIG_LOGICAL_CPUS==1
@ -112,7 +111,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "southbridge/nvidia/ck804/ck804_early_setup_car.c" #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
#include "cpu/amd/car/copy_and_run.c" #include "cpu/amd/car/copy_and_run.c"
#include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/init_cpus.c"
@ -259,10 +257,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
sio_gpio_setup(); sio_gpio_setup();
setup_mb_resource_map(); setup_mb_resource_map();
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
needs_reset = setup_coherent_ht_domain(); needs_reset = setup_coherent_ht_domain();
@ -278,7 +272,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ck804_early_setup_x(); needs_reset |= ck804_early_setup_x();
if (needs_reset) { if (needs_reset) {
printk_info("ht reset -\r\n"); printk_info("ht reset -\n");
soft_reset(); soft_reset();
} }

4
src/mainboard/tyan/s2895/resourcemap.c
View File

@ -41,7 +41,6 @@ static void setup_mb_resource_map(void)
PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005, PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006, PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007, PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
/* DRAM Base i Registers /* DRAM Base i Registers
* F1:0x40 i = 0 * F1:0x40 i = 0
* F1:0x48 i = 1 * F1:0x48 i = 1
@ -257,11 +256,8 @@ static void setup_mb_resource_map(void)
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */ PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0xff800013, /* link 0 of cpu 1 --> Nvidia CK 804 Slave */ PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0xff800013, /* link 0 of cpu 1 --> Nvidia CK 804 Slave */
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, /*113 link 1 of cpu 1 --> HT connector */ PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, /*113 link 1 of cpu 1 --> HT connector */
}; };
int max; int max;
max = ARRAY_SIZE(register_values); max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max); setup_resource_map(register_values, max);
} }

2
src/northbridge/amd/amdk8/resourcemap.c
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@ -245,7 +245,7 @@ static void setup_default_resource_map(void)
* [23:16] Bus Number Base i * [23:16] Bus Number Base i
* This field defines the lowest bus number in configuration region i * This field defines the lowest bus number in configuration region i
* [31:24] Bus Number Limit i * [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration regin i * This field defines the highest bus number in configuration region i
*/ */
PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003,
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,