White space and typo fixes. This makes it easier to compare the s2895 & s2892.
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4773 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson
parent
cb69cb3e69
commit
59b2dc2cf2
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@ -250,7 +250,6 @@ clear_fixed_var_mtrr_out:
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wrmsr
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#endif /* CONFIG_USE_FAILOVER_IMAGE == 1*/
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#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 0)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 0))
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/* disable cache */
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movl %cr0, %eax
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@ -300,7 +299,6 @@ wbcache_post_fam10_setup:
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andl $0x9fffffff, %eax
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movl %eax, %cr0
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jmp_if_k8(fam10_end_part1)
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/* So we need to check if it is BSP */
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@ -1,6 +1,12 @@
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#define ASSEMBLY 1
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#define __ROMCC__
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#define QRANK_DIMM_SUPPORT 1
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#if CONFIG_LOGICAL_CPUS==1
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#define SET_NB_CFG_54 1
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#endif
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#include <stdint.h>
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#include <string.h>
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#include <device/pci_def.h>
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@ -10,6 +16,8 @@
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#include <cpu/x86/lapic.h>
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#include "option_table.h"
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#include "pc80/mc146818rtc_early.c"
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#define post_code(x) outb(x, 0x80)
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "lib/ramtest.c"
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@ -34,10 +42,6 @@
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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static void memreset_setup(void)
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{
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}
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static void memreset(int controllers, const struct mem_controller *ctrl)
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{
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}
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@ -52,8 +56,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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return smbus_read_byte(device, address);
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}
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#define QRANK_DIMM_SUPPORT 1
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#include "northbridge/amd/amdk8/raminit.c"
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "lib/generic_sdram.c"
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@ -61,9 +63,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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/* tyan does not want the default */
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#include "resourcemap.c"
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#if CONFIG_LOGICAL_CPUS==1
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#define SET_NB_CFG_54 1
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#endif
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#include "cpu/amd/dualcore/dualcore.c"
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#define CK804_NUM 1
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@ -178,7 +177,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
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unsigned nodes;
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if (bist == 0) {
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init_cpus(cpu_init_detectedx);
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bsp_apicid = init_cpus(cpu_init_detectedx);
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}
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// post_code(0x32);
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@ -190,11 +189,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
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/* Halt if there was a built in self test failure */
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report_bist_failure(bist);
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setup_s2892_resource_map();
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#if 0
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dump_pci_device(PCI_DEV(0, 0x18, 0));
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dump_pci_device(PCI_DEV(0, 0x19, 0));
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#endif
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setup_mb_resource_map();
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needs_reset = setup_coherent_ht_domain();
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@ -210,7 +205,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
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needs_reset |= ck804_early_setup_x();
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if (needs_reset) {
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print_info("ht reset -\r\n");
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printk_info("ht reset -\n");
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soft_reset();
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}
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@ -221,23 +216,8 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
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fill_mem_ctrl(nodes, ctrl, spd_addr);
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enable_smbus();
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#if 0
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dump_spd_registers(&cpu[0]);
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#endif
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#if 0
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dump_smbus_registers();
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#endif
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memreset_setup();
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sdram_initialize(nodes, ctrl);
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#if 0
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print_pci_devices();
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#endif
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#if 0
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dump_pci_devices();
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#endif
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post_cache_as_ram();
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}
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@ -3,7 +3,7 @@
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*
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*/
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static void setup_s2892_resource_map(void)
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static void setup_mb_resource_map(void)
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{
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static const unsigned int register_values[] = {
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/* Careful set limit registers before base registers which contain the enables */
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@ -256,11 +256,8 @@ static void setup_s2892_resource_map(void)
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// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */
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PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
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};
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int max;
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max = ARRAY_SIZE(register_values);
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setup_resource_map(register_values, max);
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}
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@ -4,7 +4,6 @@
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#define K8_ALLOCATE_IO_RANGE 1
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//#define K8_SCAN_PCI_BUS 1
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//used by raminit
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#define QRANK_DIMM_SUPPORT 1
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#if CONFIG_LOGICAL_CPUS==1
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@ -112,7 +111,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
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#include "cpu/amd/car/copy_and_run.c"
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#include "cpu/amd/car/post_cache_as_ram.c"
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#include "cpu/amd/model_fxx/init_cpus.c"
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@ -259,10 +257,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
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sio_gpio_setup();
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setup_mb_resource_map();
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#if 0
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dump_pci_device(PCI_DEV(0, 0x18, 0));
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dump_pci_device(PCI_DEV(0, 0x19, 0));
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#endif
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needs_reset = setup_coherent_ht_domain();
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@ -278,7 +272,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
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needs_reset |= ck804_early_setup_x();
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if (needs_reset) {
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printk_info("ht reset -\r\n");
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printk_info("ht reset -\n");
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soft_reset();
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}
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@ -41,7 +41,6 @@ static void setup_mb_resource_map(void)
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PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
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PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
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PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
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/* DRAM Base i Registers
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* F1:0x40 i = 0
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* F1:0x48 i = 1
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@ -257,11 +256,8 @@ static void setup_mb_resource_map(void)
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PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */
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PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0xff800013, /* link 0 of cpu 1 --> Nvidia CK 804 Slave */
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PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, /*113 link 1 of cpu 1 --> HT connector */
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};
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int max;
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max = ARRAY_SIZE(register_values);
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setup_resource_map(register_values, max);
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}
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@ -245,7 +245,7 @@ static void setup_default_resource_map(void)
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* [23:16] Bus Number Base i
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* This field defines the lowest bus number in configuration region i
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* [31:24] Bus Number Limit i
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* This field defines the highest bus number in configuration regin i
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* This field defines the highest bus number in configuration region i
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*/
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PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003,
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PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
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