diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c
index fdf2605147..782f752b6c 100644
--- a/src/soc/qualcomm/ipq806x/cbmem.c
+++ b/src/soc/qualcomm/ipq806x/cbmem.c
@@ -18,10 +18,9 @@
  */
 
 #include <cbmem.h>
-#include <stddef.h>
-#include <symbols.h>
+#include <soc/soc_services.h>
 
 void *cbmem_top(void)
 {
-	return (void *)((uintptr_t)_dram + CONFIG_DRAM_SIZE_MB*MiB);
+	return _memlayout_cbmem_top;
 }
diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
index 7020f929c4..873f61cb1e 100644
--- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
@@ -39,11 +39,24 @@ SECTIONS
 	QCA_SHARED_RAM(2A03F000, 4K)
 */
 	STACK(0x2A040000, 16K)
+#ifdef __PRE_RAM__
+       /*
+        * ipq8064 is different from most other ARM platforms: it loads the
+	* proprietary DRAM initialization code from CBFS (as opposed to compiling
+	* it in into rombase). As a result CBFS needs to be used before DRAM is
+	* availale, which means CBFS cache must be in SRAM, which in turn means
+	* that PRERAM_CBFS_CACHE description can not be used here.
+	*/
 	CBFS_CACHE(0x2A044000, 96K)
+#endif
 	TTB(0x2A05C000, 16K)
 	SRAM_END(0x2A060000)
 
 	DRAM_START(0x40000000)
 	RAMSTAGE(0x40640000, 128K)
+	SYMBOL(memlayout_cbmem_top, 0x59FA0000)
+#ifndef __PRE_RAM__
+	CBFS_CACHE(0x59FA0000, 256K)
+#endif
 	DMA_COHERENT(0x5A000000, 2M)
 }
diff --git a/src/soc/qualcomm/ipq806x/include/soc/soc_services.h b/src/soc/qualcomm/ipq806x/include/soc/soc_services.h
index 8a936fe7d9..9e92bc71e3 100644
--- a/src/soc/qualcomm/ipq806x/include/soc/soc_services.h
+++ b/src/soc/qualcomm/ipq806x/include/soc/soc_services.h
@@ -20,6 +20,10 @@
 #ifndef __SOC_QUALCOMM_IPQ806X_INCLUDE_SOC_SOC_SERVICES_H__
 #define __SOC_QUALCOMM_IPQ806X_INCLUDE_SOC_SOC_SERVICES_H__
 
+#include <types.h>
+
+extern u8 _memlayout_cbmem_top[];
+
 /* Returns zero on success, nonzero on failure. */
 int initialize_dram(void);