soc/intel/fsp_broadwell_de: Add function to set DPR
Add code for FSP Broadwell DE to set the DPR. Used by the Intel TXT code. Tested on Intel Broadwell DE using Intel TXT. Change-Id: Ib5e1ba8731e5cea1be9319a1fb9658dba841dc7b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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@ -31,6 +31,15 @@ size_t sa_get_tseg_size(void);
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#define TSEG_BASE 0xa8 /* TSEG base */
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#define TSEG_LIMIT 0xac /* TSEG limit */
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#define IIO_LTDPR 0x290
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#define DPR_LOCK (1 << 0)
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#define DPR_EPM (1 << 2)
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#define DPR_PRS (1 << 1)
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#define DPR_SIZE_MASK 0xff0
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#define DPR_SIZE_SHIFT 4
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#define DPR_ADDR_MASK 0xfff00000
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#define DPR_ADDR_SHIFT 20
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/* CPU bus clock is fixed at 100MHz */
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#define CPU_BCLK 100
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@ -24,6 +24,8 @@
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void broadwell_de_init_pre_device(void);
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void broadwell_de_init_cpus(struct device *dev);
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void southcluster_enable_dev(struct device *dev);
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void broadwell_de_set_dpr(const uintptr_t addr, const size_t size);
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void broadwell_de_lock_dpr(void);
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extern struct pci_operations soc_pci_ops;
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@ -28,6 +28,7 @@
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#include <soc/pattrs.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include <soc/broadwell_de.h>
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/* Global PATTRS */
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DEFINE_PATTRS;
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@ -82,3 +83,47 @@ void broadwell_de_init_pre_device(void)
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{
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fill_in_pattrs();
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}
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/*
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* Set DPR region.
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*/
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void broadwell_de_set_dpr(const uintptr_t addr, const size_t size)
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{
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struct device *dev;
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uint32_t dpr_reg;
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/*
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* DMA Protected Range can be reserved below TSEG for PCODE patch
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* or TXT/BootGuard related data. Rather than reporting a base address
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* the DPR register reports the TOP of the region, which is the same
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* as TSEG base. The region size is reported in MiB in bits 11:4.
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*/
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dev = pcidev_on_root(VTD_DEV, VTD_FUNC);
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dpr_reg = pci_read_config32(dev, IIO_LTDPR);
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if (dpr_reg & DPR_LOCK) {
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printk(BIOS_ERR, "ERROR: HOSTBRIDGE[DPR] is already locked\n");
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return;
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}
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dpr_reg &= ~(DPR_ADDR_MASK | DPR_SIZE_MASK);
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dpr_reg |= addr & DPR_ADDR_MASK;
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dpr_reg |= (size >> (20 - DPR_SIZE_SHIFT)) & DPR_SIZE_MASK;
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dpr_reg |= DPR_EPM;
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pci_write_config32(dev, IIO_LTDPR, dpr_reg);
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}
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/*
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* Lock DPR register.
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*/
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void broadwell_de_lock_dpr(void)
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{
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struct device *dev;
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uint32_t dpr_reg;
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dev = pcidev_on_root(VTD_DEV, VTD_FUNC);
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dpr_reg = pci_read_config32(dev, IIO_LTDPR);
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if (dpr_reg & DPR_LOCK) {
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printk(BIOS_ERR, "ERROR: HOSTBRIDGE[DPR] is already locked\n");
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return;
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}
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dpr_reg |= DPR_LOCK;
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pci_write_config32(dev, IIO_LTDPR, dpr_reg);
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}
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