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rambi: enable SCI and SMI gpios 

Rambi has 3 pins that need to be configured for SCI and SMI:

1. GPIO_CORE[0] - runtime SCI pin
2. GPIO_SUS[7] - SMI for firmware lid events
3. GPIO_SUS[0] - wake pin for S3 wakes from EC.

Configure these pins now that the rest of the infrastructure
is in place. The one thing that is yet to work is runtime SCI
for lid events once booted.

BUG=chrome-os-partner:23505
BRANCH=None
TEST=built and booted. lid close at rec screen works. And wake
     from S3 with a keyboard press works.

Change-Id: I5f8e38ec5f4cf1a8ef7aa7fcee9abc344d9b184f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176393
Reviewed-on: http://review.coreboot.org/4960
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Aaron Durbin 2013-11-11 14:58:06 -06:00 committed by Aaron Durbin
parent 3fbf671194
commit 59cd6216dd
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/mainboard/google/rambi/gpio.c
View File

@ -55,7 +55,7 @@ static const struct soc_gpio_map gpncore_gpio_map[] = {
/* SCORE GPIOs */ /* SCORE GPIOs */
static const struct soc_gpio_map gpscore_gpio_map[] = { static const struct soc_gpio_map gpscore_gpio_map[] = {
GPIO_INPUT, /* S0_SC000 - SOC_KBC_SCI - INT */ GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */
GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */ GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */
GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */
GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */ GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */
@ -105,7 +105,7 @@ static const struct soc_gpio_map gpscore_gpio_map[] = {
GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */
GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */
GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */
GPIO_FUNC1, /* S0-SC050 - IRQ_SERIRQ */ GPIO_FUNC(1, PULL_UP, 10K), /* S0-SC050 - IRQ_SERIRQ */
GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */
GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */
GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */
@ -162,14 +162,14 @@ static const struct soc_gpio_map gpscore_gpio_map[] = {
/* SSUS GPIOs */ /* SSUS GPIOs */
static const struct soc_gpio_map gpssus_gpio_map[] = { static const struct soc_gpio_map gpssus_gpio_map[] = {
GPIO_NC, /* S500 - PCH_WAKE# (NC) */ GPIO_ACPI_SCI, /* S500 - PCH_WAKE# */
GPIO_FUNC6, /* S501 - TRACKPAD_INT# - INT */ GPIO_FUNC6, /* S501 - TRACKPAD_INT# - INT */
GPIO_FUNC6, /* S502 - TOUCH_INT# - INT */ GPIO_FUNC6, /* S502 - TOUCH_INT# - INT */
GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */
GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */
GPIO_NC, /* S505 - SUS_CLK_WLAN (NC) */ GPIO_NC, /* S505 - SUS_CLK_WLAN (NC) */
GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */
GPIO_INPUT, /* S507 - SOC_KBC_SMI - INT */ GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */
GPIO_NC, /* S508 - NC */ GPIO_NC, /* S508 - NC */
GPIO_NC, /* S509 - MUX_AUD_INT1# (NC) */ GPIO_NC, /* S509 - MUX_AUD_INT1# (NC) */
GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */