mainboards/google/reef: use chromeec's ASL lid switch implementation
Defer to the lid switch implementation provided by the chromeec. BUG=chrome-os-partner:56677 Change-Id: Ida451dc29c8cf55fb88015e48a9e0bca3740f645 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16733 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
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@ -46,20 +46,6 @@ DefinitionBlock(
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/* Chipset specific sleep states */
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/* Chipset specific sleep states */
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#include <soc/intel/apollolake/acpi/sleepstates.asl>
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#include <soc/intel/apollolake/acpi/sleepstates.asl>
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/* LID */
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Scope (\_SB)
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{
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Device (LID0)
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{
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Name (_HID, EisaId ("PNP0C0D"))
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Method (_LID, 0)
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{
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Return (\_SB.PCI0.LPCB.EC0.LIDS)
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}
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Name (_PRW, Package () { GPE_EC_WAKE, 0x3 })
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}
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}
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/* Chrome OS Embedded Controller */
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/* Chrome OS Embedded Controller */
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Scope (\_SB.PCI0.LPCB)
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Scope (\_SB.PCI0.LPCB)
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{
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{
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@ -16,6 +16,7 @@
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#ifndef BASEBOARD_EC_H
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#ifndef BASEBOARD_EC_H
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#define BASEBOARD_EC_H
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#define BASEBOARD_EC_H
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#include <variant/gpio.h>
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#include <ec/google/chromeec/ec_commands.h>
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#include <ec/google/chromeec/ec_commands.h>
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#define MAINBOARD_EC_SCI_EVENTS \
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#define MAINBOARD_EC_SCI_EVENTS \
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@ -64,6 +65,10 @@
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/* Enable EC backed PD MCU device in ACPI */
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/* Enable EC backed PD MCU device in ACPI */
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#define EC_ENABLE_PD_MCU_DEVICE
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#define EC_ENABLE_PD_MCU_DEVICE
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/* Enable LID switch and provide wake pin for EC */
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#define EC_ENABLE_LID_SWITCH
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#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
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#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
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#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
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#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
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#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
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#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
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#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
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