mainboards/google/reef: use chromeec's ASL lid switch implementation

Defer to the lid switch implementation provided by the chromeec.

BUG=chrome-os-partner:56677

Change-Id: Ida451dc29c8cf55fb88015e48a9e0bca3740f645
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16733
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Aaron Durbin 2016-09-23 16:08:21 -05:00
parent 05201d7783
commit 59cf5028a8
2 changed files with 5 additions and 14 deletions

View File

@ -46,20 +46,6 @@ DefinitionBlock(
/* Chipset specific sleep states */
#include <soc/intel/apollolake/acpi/sleepstates.asl>
/* LID */
Scope (\_SB)
{
Device (LID0)
{
Name (_HID, EisaId ("PNP0C0D"))
Method (_LID, 0)
{
Return (\_SB.PCI0.LPCB.EC0.LIDS)
}
Name (_PRW, Package () { GPE_EC_WAKE, 0x3 })
}
}
/* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{

View File

@ -16,6 +16,7 @@
#ifndef BASEBOARD_EC_H
#define BASEBOARD_EC_H
#include <variant/gpio.h>
#include <ec/google/chromeec/ec_commands.h>
#define MAINBOARD_EC_SCI_EVENTS \
@ -64,6 +65,10 @@
/* Enable EC backed PD MCU device in ACPI */
#define EC_ENABLE_PD_MCU_DEVICE
/* Enable LID switch and provide wake pin for EC */
#define EC_ENABLE_LID_SWITCH
#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */