AMD: Kconfig cleanup

Change-Id: I21182eae1d389790c330f27e6a830d91c3ee4eb6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3433
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This commit is contained in:
Kyösti Mälkki 2013-06-11 16:30:48 +03:00 committed by Stefan Reinauer
parent 22dcdd914c
commit 59d0d159f4
6 changed files with 22 additions and 23 deletions

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@ -24,40 +24,35 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY12
select MMCONF_SUPPORT
select NORTHBRIDGE_AMD_AGESA_FAMILY12_ROOT_COMPLEX
if NORTHBRIDGE_AMD_AGESA_FAMILY12
config HT3_SUPPORT
bool
default y
depends on NORTHBRIDGE_AMD_AGESA_FAMILY12
config HW_MEM_HOLE_SIZEK
hex
default 0x100000
depends on NORTHBRIDGE_AMD_AGESA_FAMILY12
config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n
depends on NORTHBRIDGE_AMD_AGESA_FAMILY12
config MMCONF_BASE_ADDRESS
hex
default 0xe0000000
depends on NORTHBRIDGE_AMD_AGESA_FAMILY12
config MMCONF_BUS_NUMBER
int
default 256
depends on NORTHBRIDGE_AMD_AGESA_FAMILY12
config DIMM_DDR3
bool
default n
depends on NORTHBRIDGE_AMD_AGESA_FAMILY12
config DIMM_REGISTERED
bool
default n
depends on NORTHBRIDGE_AMD_AGESA_FAMILY12
if !DIMM_REGISTERED
config DIMM_SUPPORT
@ -73,3 +68,4 @@ if DIMM_DDR3
endif
endif
endif # NORTHBRIDGE_AMD_AGESA_FAMILY_12

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@ -110,14 +110,14 @@ if DIMM_DDR3
default 0x0005
endif
endif
endif
config SVI_HIGH_FREQ
bool
default n
depends on NORTHBRIDGE_AMD_AMDFAM10
help
Select this for boards with a Voltage Regulator able to operate
at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.
endif # NORTHBRIDGE_AMD_AMDFAM10
source src/northbridge/amd/amdfam10/root_complex/Kconfig

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@ -22,12 +22,15 @@ config NORTHBRIDGE_AMD_CIMX_RD890
default n
select AMD_NB_CIMX
if NORTHBRIDGE_AMD_CIMX_RD890
config REDIRECT_NBCIMX_TRACE_TO_SERIAL
bool "Redirect AMD Northbridge CIMX Trace to serial console"
default n
depends on NORTHBRIDGE_AMD_CIMX_RD890
help
This Option allows you to redirect the AMD Northbridge CIMX
Trace debug information to the serial console.
Warning: Only enable this option when debuging or tracing AMD CIMX code.
endif # NORTHBRIDGE_AMD_CIMX_RD890

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@ -21,10 +21,11 @@ config NORTHBRIDGE_AMD_GX2
bool
select GEODE_VSA
if NORTHBRIDGE_AMD_GX2
choice
prompt "Framebuffer size"
default GX2_VIDEO_MB_8MB
depends on NORTHBRIDGE_AMD_GX2
config GX2_VIDEO_MB_4MB
bool "4MB"
@ -55,7 +56,6 @@ config VIDEO_MB
default 128 if GX2_VIDEO_MB_128MB
default 256 if GX2_VIDEO_MB_256MB
default -1 if GX2_VIDEO_MB_CMOS
depends on NORTHBRIDGE_AMD_GX2
# The GX2_PROCESSOR_MHZ options let you chose the correct GX2 processor
# speed in the mainboard's Kconfig file.
@ -73,3 +73,4 @@ config GX2_PROCESSOR_MHZ
default 366 if GX2_PROCESSOR_MHZ_366
default 400 if GX2_PROCESSOR_MHZ_400
endif # NORTHBRIDGE_AMD_GX2

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@ -22,26 +22,23 @@ config SOUTHBRIDGE_AMD_AGESA_HUDSON
select IOAPIC
select HAVE_USBDEBUG
if SOUTHBRIDGE_AMD_AGESA_HUDSON
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/amd/agesa/hudson/bootblock.c"
depends on SOUTHBRIDGE_AMD_AGESA_HUDSON
config SOUTHBRIDGE_AMD_HUDSON_SKIP_ISA_DMA_INIT
bool
default n
depends on SOUTHBRIDGE_AMD_AGESA_HUDSON
config EHCI_BAR
hex
default 0xfef00000 if SOUTHBRIDGE_AMD_AGESA_HUDSON
default 0xfef00000
config EHCI_DEBUG_OFFSET
hex
default 0xe0 if SOUTHBRIDGE_AMD_AGESA_HUDSON
if SOUTHBRIDGE_AMD_AGESA_HUDSON
default 0xe0
config HUDSON_XHCI_FWM
bool "Add xhci firmware"

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@ -23,20 +23,22 @@ config SOUTHBRIDGE_AMD_SB800
select HAVE_USBDEBUG
select HAVE_HARD_RESET
if SOUTHBRIDGE_AMD_SB800
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/amd/sb800/bootblock.c"
depends on SOUTHBRIDGE_AMD_SB800
config SOUTHBRIDGE_AMD_SB800_SKIP_ISA_DMA_INIT
bool
default n
depends on SOUTHBRIDGE_AMD_SB800
config EHCI_BAR
hex
default 0xfef00000 if SOUTHBRIDGE_AMD_SB800
default 0xfef00000
config EHCI_DEBUG_OFFSET
hex
default 0xe0 if SOUTHBRIDGE_AMD_SB800
default 0xe0
endif # SOUTHBRIDGE_AMD_SB800