mb/google/sarien: Set Vref Config to 2

Accoding to desciption in FSP header, Vref Configuration will be set to
2 if VREF_CA to CH_A and VREF_DQ_B to CH_B.

BUG=N/A
TEST=Build and boot up on Arcada platform.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I02e16e141b81d766a6060ca08283f432abd96647
Reviewed-on: https://review.coreboot.org/c/30280
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/sarien/romstage.c

@@ -37,6 +37,9 @@ static const struct cnl_mb_cfg memcfg = {
 
 	/* Disable Early Command Training */
 	.ect = 0,
+
+	/* Base on board design */
+	.vref_ca_config = 2,
 };
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)