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mb/google/sarien: Set Vref Config to 2 

Accoding to desciption in FSP header, Vref Configuration will be set to
2 if VREF_CA to CH_A and VREF_DQ_B to CH_B.

BUG=N/A
TEST=Build and boot up on Arcada platform.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I02e16e141b81d766a6060ca08283f432abd96647
Reviewed-on: https://review.coreboot.org/c/30280
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Lijian Zhao 2018-12-17 10:03:05 -08:00 committed by Duncan Laurie
parent 51122920e8
commit 59de870aa3
1 changed files with 3 additions and 0 deletions
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3
src/mainboard/google/sarien/romstage.c
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@ -37,6 +37,9 @@ static const struct cnl_mb_cfg memcfg = {
/* Disable Early Command Training */ /* Disable Early Command Training */
.ect = 0, .ect = 0,
/* Base on board design */
.vref_ca_config = 2,
}; };
void mainboard_memory_init_params(FSPM_UPD *memupd) void mainboard_memory_init_params(FSPM_UPD *memupd)