AGESA: Switch to MMCONF_SUPPORT_DEFAULT

Vendorcode always does PCI MMCONF access once it is
enabled via MSR.

In coreboot proper, we don't give opportunity to make
pci_read/write calls before PCI MMCONF is enabled via MSR.
This happens early in romstage amd_initmmio() for all cores.

Change-Id: If31bc0a67b480bcc1d955632f413f5cdeec51a54
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17533
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/cpu/amd/agesa/family10/Kconfig

@@ -17,6 +17,7 @@ config CPU_AMD_AGESA_FAMILY10
 	bool
 	select CPU_AMD_MODEL_10XXX
 	select PCI_IO_CFG_EXT
+	select MMCONF_SUPPORT_DEFAULT
 	select X86_AMD_FIXED_MTRRS
 
 if CPU_AMD_AGESA_FAMILY10

src/cpu/amd/agesa/family12/Kconfig

@@ -16,6 +16,7 @@
 config CPU_AMD_AGESA_FAMILY12
 	bool
 	select PCI_IO_CFG_EXT
+	select MMCONF_SUPPORT_DEFAULT
 	select X86_AMD_FIXED_MTRRS
 
 if CPU_AMD_AGESA_FAMILY12

src/cpu/amd/agesa/family14/Kconfig

@@ -16,6 +16,7 @@
 config CPU_AMD_AGESA_FAMILY14
 	bool
 	select PCI_IO_CFG_EXT
+	select MMCONF_SUPPORT_DEFAULT
 	select X86_AMD_FIXED_MTRRS
 
 if CPU_AMD_AGESA_FAMILY14

src/cpu/amd/agesa/family15/Kconfig

@@ -16,6 +16,7 @@
 config CPU_AMD_AGESA_FAMILY15
 	bool
 	select PCI_IO_CFG_EXT
+	select MMCONF_SUPPORT_DEFAULT
 	select X86_AMD_FIXED_MTRRS
 
 if CPU_AMD_AGESA_FAMILY15

src/cpu/amd/agesa/family15rl/Kconfig

@@ -17,6 +17,7 @@
 config CPU_AMD_AGESA_FAMILY15_RL
 	bool
 	select PCI_IO_CFG_EXT
+	select MMCONF_SUPPORT_DEFAULT
 	select X86_AMD_FIXED_MTRRS
 
 if CPU_AMD_AGESA_FAMILY15_RL

src/cpu/amd/agesa/family15tn/Kconfig

@@ -16,6 +16,7 @@
 config CPU_AMD_AGESA_FAMILY15_TN
 	bool
 	select PCI_IO_CFG_EXT
+	select MMCONF_SUPPORT_DEFAULT
 	select X86_AMD_FIXED_MTRRS
 
 if CPU_AMD_AGESA_FAMILY15_TN

src/cpu/amd/agesa/family16kb/Kconfig

@@ -16,6 +16,7 @@
 config CPU_AMD_AGESA_FAMILY16_KB
 	bool
 	select PCI_IO_CFG_EXT
+	select MMCONF_SUPPORT_DEFAULT
 	select X86_AMD_FIXED_MTRRS
 
 if CPU_AMD_AGESA_FAMILY16_KB

src/mainboard/amd/dinar/romstage.c

@@ -39,6 +39,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
+	/* Must come first to enable PCI MMCONF. */
 	amd_initmmio();
 
 	if (!cpu_init_detectedx && boot_cpu()) {

src/mainboard/amd/inagua/romstage.c

@@ -40,6 +40,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
+	/* Must come first to enable PCI MMCONF. */
 	amd_initmmio();
 
 	if (!cpu_init_detectedx && boot_cpu()) {

src/mainboard/amd/olivehill/romstage.c

@@ -38,6 +38,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
+	/* Must come first to enable PCI MMCONF. */
+	amd_initmmio();
+
 	/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
 	 *  LpcClk[1:0]".  To be consistent with Parmer, setting to 4mA
 	 *  even though the register is not documented in the Kabini BKDG.
@@ -46,8 +49,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	outb(0xD2, 0xcd6);
 	outb(0x00, 0xcd7);
 
-	amd_initmmio();
-
 	/* Set LPC decode enables. */
 	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
 	pci_write_config32(dev, 0x44, 0xff03ffd5);

src/mainboard/amd/parmer/romstage.c

@@ -38,6 +38,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
+	/* Must come first to enable PCI MMCONF. */
 	amd_initmmio();
 
 	/* Set LPC decode enables. */

src/mainboard/amd/persimmon/romstage.c

@@ -46,6 +46,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
+	/* Must come first to enable PCI MMCONF. */
 	amd_initmmio();
 
 	if (!cpu_init_detectedx && boot_cpu()) {

src/mainboard/amd/south_station/romstage.c

@@ -41,6 +41,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
+	/* Must come first to enable PCI MMCONF. */
 	amd_initmmio();
 
 	if (!cpu_init_detectedx && boot_cpu()) {

src/mainboard/amd/thatcher/romstage.c

@@ -43,6 +43,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u8 byte;
 	pci_devfn_t dev;
 
+	/* Must come first to enable PCI MMCONF. */
 	amd_initmmio();
 
 	/* Set LPC decode enables. */

src/mainboard/amd/torpedo/romstage.c

@@ -39,9 +39,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-	post_code(0x35);
+	/* Must come first to enable PCI MMCONF. */
 	amd_initmmio();
 
+	post_code(0x35);
+
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x30);
 		gpioEarlyInit();

src/mainboard/amd/union_station/romstage.c

@@ -39,6 +39,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
+	/* Must come first to enable PCI MMCONF. */
 	amd_initmmio();
 
 	if (!cpu_init_detectedx && boot_cpu()) {

src/mainboard/asrock/e350m1/romstage.c

@@ -43,6 +43,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
+	/* Must come first to enable PCI MMCONF. */
 	amd_initmmio();
 
 	if (!cpu_init_detectedx && boot_cpu()) {

src/mainboard/asrock/imb-a180/romstage.c

@@ -51,6 +51,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	//outb(0xD2, 0xcd6);
 	//outb(0x00, 0xcd7);
 
+	/* Must come first to enable PCI MMCONF. */
 	amd_initmmio();
 
 	/* Set LPC decode enables. */

src/mainboard/asus/f2a85-m/romstage.c

@@ -64,6 +64,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u8 byte;
 	pci_devfn_t dev;
 
+	/* Must come first to enable PCI MMCONF. */
 	amd_initmmio();
 
 #if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE)

src/mainboard/bap/ode_e20XX/romstage.c

@@ -43,6 +43,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
+	/* Must come first to enable PCI MMCONF. */
 	amd_initmmio();
 
 	/* Set LPC decode enables. */

src/mainboard/biostar/am1ml/romstage.c

@@ -113,6 +113,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	pci_devfn_t dev;
 	u32 *addr32;
 
+	/* Must come first to enable PCI MMCONF. */
+	amd_initmmio();
+
 	/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
 	 * LpcClk[1:0]".  To be consistent with Parmer, setting to 4mA
 	 * even though the register is not documented in the Kabini BKDG.
@@ -121,7 +124,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	outb(0xD2, 0xcd6);
 	outb(0x00, 0xcd7);
 
-	amd_initmmio();
 	/* Set LPC decode enables. */
 	pci_devfn_t dev2 = PCI_DEV(0, 0x14, 3);
 	pci_write_config32(dev2, 0x44, 0xff03ffd5);

src/mainboard/elmex/pcm205400/romstage.c

@@ -46,6 +46,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
+	/* Must come first to enable PCI MMCONF. */
 	amd_initmmio();
 
 	if (!cpu_init_detectedx && boot_cpu()) {

src/mainboard/gizmosphere/gizmo/romstage.c

@@ -41,6 +41,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
+	/* Must come first to enable PCI MMCONF. */
 	amd_initmmio();
 
 	if (!cpu_init_detectedx && boot_cpu()) {

src/mainboard/gizmosphere/gizmo2/romstage.c

@@ -38,6 +38,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
+	/* Must come first to enable PCI MMCONF. */
+	amd_initmmio();
+
 	/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
 	 *  LpcClk[1:0]".  To be consistent with Parmer, setting to 4mA
 	 *  even though the register is not documented in the Kabini BKDG.
@@ -46,8 +49,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	outb(0xD2, 0xcd6);
 	outb(0x00, 0xcd7);
 
-	amd_initmmio();
-
 	/* Set LPC decode enables. */
 	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
 	pci_write_config32(dev, 0x44, 0xff03ffd5);

src/mainboard/hp/abm/romstage.c

@@ -44,6 +44,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u32 *addr32;
 
 
+	/* Must come first to enable PCI MMCONF. */
 	amd_initmmio();
 
 	/* Set LPC decode enables. */

src/mainboard/hp/pavilion_m6_1035dx/romstage.c

@@ -34,6 +34,8 @@
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
+
+	/* Must come first to enable PCI MMCONF. */
 	amd_initmmio();
 
 	hudson_lpc_port80();

src/mainboard/jetway/nf81-t56n-lf/romstage.c

@@ -62,6 +62,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
+	/* Must come first to enable PCI MMCONF. */
 	amd_initmmio();
 
 	if (!cpu_init_detectedx && boot_cpu()) {

src/mainboard/lenovo/g505s/romstage.c

@@ -34,6 +34,8 @@
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
+
+	/* Must come first to enable PCI MMCONF. */
 	amd_initmmio();
 
 	hudson_lpc_port80();

src/mainboard/lippert/frontrunner-af/romstage.c

@@ -45,6 +45,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
+	/* Must come first to enable PCI MMCONF. */
 	amd_initmmio();
 
 	if (!cpu_init_detectedx && boot_cpu()) {

src/mainboard/lippert/toucan-af/romstage.c

@@ -46,6 +46,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
+	/* Must come first to enable PCI MMCONF. */
 	amd_initmmio();
 
 	if (!cpu_init_detectedx && boot_cpu()) {

src/mainboard/msi/ms7721/romstage.c

@@ -128,6 +128,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u8 byte;
 	pci_devfn_t dev;
 
+	/* Must come first to enable PCI MMCONF. */
 	amd_initmmio();
 
 #if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE)

src/mainboard/pcengines/apu1/romstage.c

@@ -51,6 +51,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
+	/* Must come first to enable PCI MMCONF. */
 	amd_initmmio();
 
 	if (!cpu_init_detectedx && boot_cpu()) {

src/mainboard/supermicro/h8qgi/Kconfig

@@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_MP_TABLE
 	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_2048
-	#select MMCONF_SUPPORT_DEFAULT #TODO enable it to resolve Multicore IO conflict
 
 config MAINBOARD_DIR
 	string

src/mainboard/supermicro/h8qgi/romstage.c

@@ -40,8 +40,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-	post_code(0x30);
+	/* Must come first to enable PCI MMCONF. */
 	amd_initmmio();
+
 	post_code(0x31);
 
 	/* Halt if there was a built in self test failure */

src/mainboard/supermicro/h8scm/romstage.c

@@ -39,8 +39,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-	post_code(0x30);
+	/* Must come first to enable PCI MMCONF. */
 	amd_initmmio();
+
 	post_code(0x31);
 
 	/* Halt if there was a built in self test failure */

src/mainboard/tyan/s8226/Kconfig

@@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_MP_TABLE
 	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_4096
-	#select MMCONF_SUPPORT_DEFAULT #TODO enable it to resolve Multicore IO conflict
 
 config MAINBOARD_DIR
 	string

src/mainboard/tyan/s8226/romstage.c

@@ -38,8 +38,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-	post_code(0x30);
+	/* Must come first to enable PCI MMCONF. */
 	amd_initmmio();
+
 	post_code(0x31);
 
 	/* For serial port. */

src/northbridge/amd/agesa/family10/Kconfig

@@ -18,7 +18,6 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY10
 	select HAVE_DEBUG_RAM_SETUP
 	select HAVE_DEBUG_SMBUS
 	select HYPERTRANSPORT_PLUGIN_SUPPORT
-	select MMCONF_SUPPORT
 
 if NORTHBRIDGE_AMD_AGESA_FAMILY10
 

src/northbridge/amd/agesa/family10/northbridge.c

@@ -1096,13 +1096,11 @@ static void cpu_bus_init(device_t dev)
 
 static void cpu_bus_read_resources(device_t dev)
 {
-#if CONFIG_MMCONF_SUPPORT
 	struct resource *resource = new_resource(dev, 0xc0010058);
 	resource->base = CONFIG_MMCONF_BASE_ADDRESS;
 	resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256;
 	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
 		IORESOURCE_FIXED | IORESOURCE_STORED |  IORESOURCE_ASSIGNED;
-#endif
 }
 
 static void cpu_bus_set_resources(device_t dev)

src/northbridge/amd/agesa/family12/Kconfig

@@ -17,7 +17,6 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY12
 	select HAVE_DEBUG_RAM_SETUP
 	select HAVE_DEBUG_SMBUS
 	select HYPERTRANSPORT_PLUGIN_SUPPORT
-	select MMCONF_SUPPORT
 
 if NORTHBRIDGE_AMD_AGESA_FAMILY12
 

src/northbridge/amd/agesa/family12/northbridge.c

@@ -649,13 +649,11 @@ static void cpu_bus_read_resources(device_t dev)
 {
 	printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
 
-#if CONFIG_MMCONF_SUPPORT
 	struct resource *resource = new_resource(dev, 0xc0010058);
 	resource->base = CONFIG_MMCONF_BASE_ADDRESS;
 	resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256;
 	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
 		IORESOURCE_FIXED | IORESOURCE_STORED |  IORESOURCE_ASSIGNED;
-#endif
 	printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);
 }
 

src/northbridge/amd/agesa/family14/Kconfig

@@ -14,7 +14,6 @@
 ##
 config NORTHBRIDGE_AMD_AGESA_FAMILY14
 	bool
-	select MMCONF_SUPPORT
 
 if NORTHBRIDGE_AMD_AGESA_FAMILY14
 

src/northbridge/amd/agesa/family14/northbridge.c

@@ -302,13 +302,11 @@ static void nb_read_resources(device_t dev)
 	 * It is not honored by the coreboot resource allocator if it is in
 	 * the CPU_CLUSTER.
 	 */
-#if CONFIG_MMCONF_SUPPORT
 	struct resource *resource = new_resource(dev, 0xc0010058);
 	resource->base = CONFIG_MMCONF_BASE_ADDRESS;
 	resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256;
 	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
 	    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-#endif
 }
 
 static void set_resource(device_t dev, struct resource *resource, u32 nodeid)

src/northbridge/amd/agesa/family15/Kconfig

@@ -18,7 +18,6 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY15
 	select HAVE_DEBUG_RAM_SETUP
 	select HAVE_DEBUG_SMBUS
 	select HYPERTRANSPORT_PLUGIN_SUPPORT
-	select MMCONF_SUPPORT
 
 if NORTHBRIDGE_AMD_AGESA_FAMILY15
 

src/northbridge/amd/agesa/family15/northbridge.c

@@ -326,13 +326,11 @@ static void nb_read_resources(device_t dev)
 	 * It is not honored by the coreboot resource allocator if it is in
 	 * the CPU_CLUSTER.
 	 */
-#if CONFIG_MMCONF_SUPPORT
 	struct resource *resource = new_resource(dev, 0xc0010058);
 	resource->base = CONFIG_MMCONF_BASE_ADDRESS;
 	resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256;
 	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
 	    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-#endif
 }
 
 static void set_resource(device_t dev, struct resource *resource, u32 nodeid)

src/northbridge/amd/agesa/family15rl/Kconfig

@@ -14,7 +14,6 @@
 ##
 config NORTHBRIDGE_AMD_AGESA_FAMILY15_RL
 	bool
-	select MMCONF_SUPPORT
 
 if NORTHBRIDGE_AMD_AGESA_FAMILY15_RL
 

src/northbridge/amd/agesa/family15rl/northbridge.c

@@ -326,13 +326,11 @@ static void read_resources(struct device *dev)
 	 * It is not honored by the coreboot resource allocator if it is in
 	 * the CPU_CLUSTER.
 	 */
-#if CONFIG_MMCONF_SUPPORT
 	struct resource *resource = new_resource(dev, 0xc0010058);
 	resource->base = CONFIG_MMCONF_BASE_ADDRESS;
 	resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256;
 	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
 	    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-#endif
 }
 
 static void set_resource(struct device *dev, struct resource *resource, u32 nodeid)

src/northbridge/amd/agesa/family15tn/Kconfig

@@ -14,7 +14,6 @@
 ##
 config NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
 	bool
-	select MMCONF_SUPPORT
 
 if NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
 

src/northbridge/amd/agesa/family15tn/northbridge.c

@@ -325,13 +325,11 @@ static void nb_read_resources(device_t dev)
 	 * It is not honored by the coreboot resource allocator if it is in
 	 * the CPU_CLUSTER.
 	 */
-#if CONFIG_MMCONF_SUPPORT
 	struct resource *resource = new_resource(dev, 0xc0010058);
 	resource->base = CONFIG_MMCONF_BASE_ADDRESS;
 	resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256;
 	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
 	    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-#endif
 }
 
 static void set_resource(device_t dev, struct resource *resource, u32 nodeid)

src/northbridge/amd/agesa/family16kb/Kconfig

@@ -15,7 +15,6 @@
 ##
 config NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
 	bool
-	select MMCONF_SUPPORT
 
 if NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
 

src/northbridge/amd/agesa/family16kb/northbridge.c

@@ -325,13 +325,11 @@ static void read_resources(device_t dev)
 	 * It is not honored by the coreboot resource allocator if it is in
 	 * the APIC_CLUSTER.
 	 */
-#if CONFIG_MMCONF_SUPPORT
 	struct resource *resource = new_resource(dev, 0xc0010058);
 	resource->base = CONFIG_MMCONF_BASE_ADDRESS;
 	resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256;
 	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
 		IORESOURCE_FIXED | IORESOURCE_STORED |  IORESOURCE_ASSIGNED;
-#endif
 }
 
 static void set_resource(device_t dev, struct resource *resource, u32 nodeid)