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baytrail: initialize backlight PWM frequency 

In order to protect ourselves from the kernel driver not honoring or
placing the correct frequency in the backlight register always set one.
This code path picks 200Hz as the default if nothing is specified in
device tree. It's somewhat arbitrary but that frequency is valid for all
the eDP panel specs we've seen being used on baytrail devices.

BUG=chrome-os-partner:28267
BRANCH=baytrail
TEST=Built and booted in normal mode. Noted register write stuck.

Original-Change-Id: Ifec29f0671e9f14ba57b9643c29d8bb2cd07eef5
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/196821
Original-Reviewed-by: Marc Jones <marc.jones@se-eng.com>
(cherry picked from commit 2eaa650860ebbc838dbf8c1c1ca2259ac64141ac)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ifec29f0671e9f14ba57b9643c29d8bb2cd07eef5
Reviewed-on: http://review.coreboot.org/7845
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Aaron Durbin 2014-04-24 11:35:28 -05:00 committed by Marc Jones
parent a081305729
commit 59e209af89
2 changed files with 27 additions and 0 deletions
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2
src/soc/intel/baytrail/chip.h
View File

@ -78,6 +78,7 @@ struct soc_intel_baytrail_config {
uint16_t gpu_pipea_power_off_delay; uint16_t gpu_pipea_power_off_delay;
uint16_t gpu_pipea_light_off_delay; uint16_t gpu_pipea_light_off_delay;
uint16_t gpu_pipea_power_cycle_delay; uint16_t gpu_pipea_power_cycle_delay;
int gpu_pipea_pwm_freq_hz;
int gpu_pipeb_port_select; /* Port select: 1=DP_B 2=DP_C */ int gpu_pipeb_port_select; /* Port select: 1=DP_B 2=DP_C */
uint16_t gpu_pipeb_power_on_delay; uint16_t gpu_pipeb_power_on_delay;
@ -85,6 +86,7 @@ struct soc_intel_baytrail_config {
uint16_t gpu_pipeb_power_off_delay; uint16_t gpu_pipeb_power_off_delay;
uint16_t gpu_pipeb_light_off_delay; uint16_t gpu_pipeb_light_off_delay;
uint16_t gpu_pipeb_power_cycle_delay; uint16_t gpu_pipeb_power_cycle_delay;
int gpu_pipeb_pwm_freq_hz;
}; };
extern struct chip_operations soc_intel_baytrail_ops; extern struct chip_operations soc_intel_baytrail_ops;

25
src/soc/intel/baytrail/gfx.c
View File

@ -290,6 +290,27 @@ static void gfx_post_vbios_init(device_t dev)
gfx_run_script(dev, gfx_post_vbios_script); gfx_run_script(dev, gfx_post_vbios_script);
} }
static void set_backlight_pwm(device_t dev, uint32_t bklt_reg, int req_hz)
{
int divider;
struct resource *res;
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res == NULL)
return;
/* Default to 200 Hz if nothing is set. */
if (req_hz == 0)
req_hz = 200;
/* Base clock is 25MHz */
divider = 25 * 1000 * 1000 / (16 * req_hz);
/* Do not set duty cycle (lower 16 bits). Just set the divider. */
write32(res->base + bklt_reg, divider << 16);
}
static void gfx_panel_setup(device_t dev) static void gfx_panel_setup(device_t dev)
{ {
struct soc_intel_baytrail_config *config = dev->chip_info; struct soc_intel_baytrail_config *config = dev->chip_info;
@ -333,11 +354,15 @@ static void gfx_panel_setup(device_t dev)
if (config->gpu_pipea_port_select) { if (config->gpu_pipea_port_select) {
printk(BIOS_INFO, "GFX: Initialize PIPEA\n"); printk(BIOS_INFO, "GFX: Initialize PIPEA\n");
reg_script_run_on_dev(dev, gfx_pipea_init); reg_script_run_on_dev(dev, gfx_pipea_init);
set_backlight_pwm(dev, PIPEA_REG(BACKLIGHT_CTL),
config->gpu_pipea_pwm_freq_hz);
} }
if (config->gpu_pipeb_port_select) { if (config->gpu_pipeb_port_select) {
printk(BIOS_INFO, "GFX: Initialize PIPEB\n"); printk(BIOS_INFO, "GFX: Initialize PIPEB\n");
reg_script_run_on_dev(dev, gfx_pipeb_init); reg_script_run_on_dev(dev, gfx_pipeb_init);
set_backlight_pwm(dev, PIPEB_REG(BACKLIGHT_CTL),
config->gpu_pipeb_pwm_freq_hz);
} }
} }