tegra124: modify panel init sequence

Panel datasheet defines some delay between PWM signal out and
backlight enable. This change fixes the current sequence
and makes the delays adjustable by dt setting.

BRANCH=none
BUG=chrome-os-partner:28008
TEST=Verified on Big DVT and Nyan/Norrin panels.
     Panel works fine with dev mode, and the measurement
     of power on sequence meets panel requirements.

Original-Change-Id: If6015bbb6015a3b203d425f5e90f676ad786b5e8
Original-Signed-off-by: Ken Chang <kenc@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/196183
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit 2bbcaa7281222ffc0b4026e8b1eb4c210a8e308a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Id6424f66eb8dc6adeb70eaa33df742f4e57983c3
Reviewed-on: http://review.coreboot.org/7776
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)

src/mainboard/google/nyan/devicetree.cb

@@ -47,6 +47,7 @@ chip soc/nvidia/tegra124
 
 	# various panel delay time
 	register "vdd_delay_ms" = "200"
+	register "pwm_to_bl_delay_ms" = "10"
 	register "vdd_to_hpd_delay_ms" = "200"
 	register "hpd_unplug_min_us" = "2000"
 	register "hpd_plug_min_us" = "250"

src/mainboard/google/nyan_big/devicetree.cb

@@ -47,6 +47,7 @@ chip soc/nvidia/tegra124
 
 	# various panel delay time
 	register "vdd_delay_ms" = "200"
+	register "pwm_to_bl_delay_ms" = "10"
 	register "vdd_to_hpd_delay_ms" = "200"
 	register "hpd_unplug_min_us" = "2000"
 	register "hpd_plug_min_us" = "250"

src/mainboard/google/nyan_blaze/devicetree.cb

@@ -47,6 +47,7 @@ chip soc/nvidia/tegra124
 
 	# various panel delay time
 	register "vdd_delay_ms" = "200"
+	register "pwm_to_bl_delay_ms" = "10"
 	register "vdd_to_hpd_delay_ms" = "200"
 	register "hpd_unplug_min_us" = "2000"
 	register "hpd_plug_min_us" = "250"

src/soc/nvidia/tegra124/chip.h

@@ -72,6 +72,9 @@ struct soc_nvidia_tegra124_config {
 	/* Delay before from power on asserting vdd */
 	int vdd_delay_ms;
 
+	/* Delay beween pwm and backlight_en_gpio is asserted */
+	int pwm_to_bl_delay_ms;
+
 	/* Delay before HPD high */
 	int vdd_to_hpd_delay_ms;
 

src/soc/nvidia/tegra124/display.c

@@ -252,20 +252,6 @@ void display_startup(device_t dev)
 		printk(BIOS_SPEW,"%s: lvds shutdown setting gpio %08x to %d\n",
 			__func__, config->lvds_shutdown_gpio, 0);
 	}
-	if (config->backlight_en_gpio){
-		gpio_output(config->backlight_en_gpio, 1);
-		printk(BIOS_SPEW,"%s: backlight enable setting gpio %08x to %d\n",
-			__func__, config->backlight_en_gpio, 1);
-	}
-
-	/* Set up Tegra PWM n (where n is specified in config->pwm) to drive the
-	 * panel backlight.
-	 */
-	printk(BIOS_SPEW, "%s: enable panel backlight pwm\n", __func__);
-	WRITEL(((1 << NV_PWM_CSR_ENABLE_SHIFT) |
-		(220 << NV_PWM_CSR_PULSE_WIDTH_SHIFT) | /* 220/256 */
-		0x02e), /* frequency divider */
-	       &pwm->pwm[config->pwm].csr);
 
 	if (framebuffer_size_mb == 0){
 		framebuffer_size_mb = ALIGN_UP(config->xres * config->yres *
@@ -313,6 +299,22 @@ void display_startup(device_t dev)
 
 	update_window(disp_ctrl, config);
 
+	/* Set up Tegra PWM n (where n is specified in config->pwm) to drive the
+	 * panel backlight.
+	 */
+	printk(BIOS_SPEW, "%s: enable panel backlight pwm\n", __func__);
+	WRITEL(((1 << NV_PWM_CSR_ENABLE_SHIFT) |
+		(220 << NV_PWM_CSR_PULSE_WIDTH_SHIFT) | /* 220/256 */
+		0x02e), /* frequency divider */
+	       &pwm->pwm[config->pwm].csr);
+
+	udelay(config->pwm_to_bl_delay_ms * 1000);
+	if (config->backlight_en_gpio){
+		gpio_output(config->backlight_en_gpio, 1);
+		printk(BIOS_SPEW,"%s: backlight enable setting gpio %08x to %d\n",
+			__func__, config->backlight_en_gpio, 1);
+	}
+
 	printk(BIOS_INFO, "%s: display init done.\n", __func__);
 
 	/* tell depthcharge ...