mb/google/brask/variants/moli: init overridetree for moli
init overridetree.cb based on the schematic adl_rfq_mb_20220310.pdf BUG=b:220814038 Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I8829d4b39d48ae574eeccbfc62e79b671211ae2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Raihow Shi
Tim Wawrzynczak
parent
f613ce0479
commit
5a0ad11868
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@ -1,6 +1,232 @@
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fw_config
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field DB_OPT 2 3
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option OPT_ABSENT 0
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option OPT_HDMI 1
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option OPT_DP 2
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end
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end
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chip soc/intel/alderlake
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chip soc/intel/alderlake
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# Enable HDMI2 in PortA, HDMI1 in PortB, HDMI/DP in Port2
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device domain 0 on
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register "ddi_ports_config" = "{
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end
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[DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
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[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
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[DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
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}"
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register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_Type-A Port A2
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register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # USB2_Type-A Port A3
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register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2_Type-A Port A9
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register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable TCP3
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register "CnviBtAudioOffload" = "true"
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device domain 0 on
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device ref tcss_dma0 on
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chip drivers/intel/usb4/retimer
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register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
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use tcss_usb3_port1 as dfp[0].typec_port
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device generic 0 on end
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end
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end
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device ref pcie4_0 on
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# Enable CPU PCIE RP 1 using CLK 0
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register "cpu_pcie_rp[CPU_RP(1)]" = "{
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.clk_req = 0,
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.clk_src = 0,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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end # SSD gen4
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device ref cnvi_wifi on
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chip drivers/wifi/generic
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register "wake" = "GPE0_PME_B0"
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device generic 0 on end
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end
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end # WiFi
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device ref i2c0 on
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chip drivers/i2c/nau8825
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register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)"
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register "jkdet_enable" = "1"
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register "jkdet_pull_enable" = "0"
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register "jkdet_pull_up" = "0"
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register "jkdet_polarity" = "1" # ActiveLow
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register "vref_impedance" = "2" # 125kOhm
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register "micbias_voltage" = "6" # 2.754
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register "sar_threshold_num" = "4"
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register "sar_threshold[0]" = "0x0C"
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register "sar_threshold[1]" = "0x1C"
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register "sar_threshold[2]" = "0x38"
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register "sar_threshold[3]" = "0x60"
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register "sar_hysteresis" = "1"
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register "sar_voltage" = "6"
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register "sar_compare_time" = "0" # 500ns
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register "sar_sampling_time" = "0" # 2us
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register "short_key_debounce" = "2" # 100ms
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register "jack_insert_debounce" = "7" # 512ms
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register "jack_eject_debounce" = "7" # 512ms
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device i2c 1a on end
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end
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end # Audio Nau8825
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device ref pcie_rp6 on
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# Enable PCIe-to-i225 bridge PCIe 6 using clk 5
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register "pch_pcie_rp[PCH_RP(6)]" = "{
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.clk_src = 5,
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.clk_req = 5,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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device pci 00.0 on end
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end # IntelI225V Ethernet NIC
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device ref pcie_rp7 on
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chip drivers/net
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register "customized_leds" = "0x05af"
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register "wake" = "GPE0_DW0_07"
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register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H22)"
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register "stop_delay_ms" = "12" # NIC needs time to quiesce
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register "stop_off_delay_ms" = "1"
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register "has_power_resource" = "1"
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register "device_index" = "0"
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device pci 00.0 on end
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end
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end # RTL8111K Ethernet NIC
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device ref pcie_rp8 on
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chip soc/intel/common/block/pcie/rtd3
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)"
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register "srcclk_pin" = "3"
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device generic 0 on end
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end
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end # PCIE8 SD card
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device ref pcie_rp9 off end #pcie_rp 9 Empty
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device ref pcie_rp10 off end #pcie_rp 10 Empty
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device ref pcie_rp11 off end #pcie_rp 11 Empty
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device ref pcie_rp12 on
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chip soc/intel/common/block/pcie/rtd3
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E20)"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)"
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register "srcclk_pin" = "1"
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device generic 0 alias emmc_rtd3 on end
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end # Enable PCIe-to-eMMC bridge PCIE 12 using clk 1
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register "pch_pcie_rp[PCH_RP(12)]" = "{
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.clk_src = 1,
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.clk_req = 1,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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end # PCIE12 BH799BB
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device ref pch_espi on
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chip ec/google/chromeec
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use conn0 as mux_conn[0]
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device pnp 0c09.0 on end
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end
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end
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device ref pmc hidden
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chip drivers/intel/pmc_mux
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device generic 0 on
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chip drivers/intel/pmc_mux/conn
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use usb2_port1 as usb2_port
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use tcss_usb3_port1 as usb3_port
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device generic 0 alias conn0 on end
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end
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end
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end
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end
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device ref tcss_xhci on
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chip drivers/usb/acpi
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device ref tcss_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C0 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))"
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device ref tcss_usb3_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C2 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, RIGHT, ACPI_PLD_GROUP(2, 1))"
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device ref tcss_usb3_port2 on end
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end
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end
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end
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end
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device ref xhci on
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chip drivers/usb/acpi
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device ref xhci_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C0 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))"
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device ref usb2_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C2 (MLB)""
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register "type" = "UPC_TYPE_A"
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register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(2, 1))"
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device ref usb2_port3 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port A4 (MLB)""
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register "type" = "UPC_TYPE_A"
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register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(4, 1))"
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device ref usb2_port4 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 NFC""
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register "type" = "UPC_TYPE_INTERNAL"
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device ref usb2_port5 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port A3 (MLB)""
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register "type" = "UPC_TYPE_A"
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register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 1))"
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device ref usb2_port6 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port A2 (MLB)""
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register "type" = "UPC_TYPE_A"
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register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(6, 1))"
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device ref usb2_port7 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port A1 (MLB)""
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register "type" = "UPC_TYPE_A"
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register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(7, 1))"
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device ref usb2_port8 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Bluetooth""
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register "type" = "UPC_TYPE_INTERNAL"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
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device ref usb2_port10 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Port A1 (MLB)""
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register "type" = "UPC_TYPE_USB3_A"
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register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(7, 2))"
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device ref usb3_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Port A2 (MLB)""
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register "type" = "UPC_TYPE_USB3_A"
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register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(6, 1))"
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device ref usb3_port2 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Port A3 (MLB)""
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register "type" = "UPC_TYPE_USB3_A"
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register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 1))"
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device ref usb3_port3 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Port A4 (MLB)""
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register "type" = "UPC_TYPE_USB3_A"
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register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(4, 1))"
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device ref usb3_port4 on end
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end
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end
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end
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end #USB2 and USB3 Port
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device ref i2c1 on
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chip drivers/i2c/tpm
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register "hid" = ""GOOG0005""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
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device i2c 50 on end
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end
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end # tpm
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end
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end
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end
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