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soc/intel/common/thermal: Use `clrsetbits32()` for setting LTT 

This patch uses `clrsetbits32` helper function to set thermal
device Low Temp Threshold (LTT) value.

BUG=b:193774296
TEST=Able to build and boot hatch and adlrvp with this change.

Change-Id: I51fea7bd2146ea29ef476218c006f7350b32c006
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59310
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2021-11-17 15:26:24 +05:30
parent ca247629da
commit 5a13d6617c
1 changed files with 1 additions and 6 deletions
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7
src/soc/intel/common/block/thermal/thermal.c
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@ -40,7 +40,6 @@ static uint32_t pch_get_ltt_value(void)
/* Enable thermal sensor power management */ /* Enable thermal sensor power management */
void pch_thermal_configuration(void) void pch_thermal_configuration(void)
{ {
uint16_t reg16;
uintptr_t thermalbar; uintptr_t thermalbar;
uintptr_t thermalbar_pm; uintptr_t thermalbar_pm;
const struct device *dev; const struct device *dev;
@ -65,9 +64,5 @@ void pch_thermal_configuration(void)
thermalbar_pm = thermalbar + THERMAL_SENSOR_POWER_MANAGEMENT; thermalbar_pm = thermalbar + THERMAL_SENSOR_POWER_MANAGEMENT;
/* Set Low Temp Threshold (LTT) at TSPM offset 0x1c[8:0] */ /* Set Low Temp Threshold (LTT) at TSPM offset 0x1c[8:0] */
reg16 = read16((uint16_t *)thermalbar_pm); clrsetbits32((void *)thermalbar_pm, CATASTROPHIC_TRIP_POINT_MASK, pch_get_ltt_value());
reg16 &= ~CATASTROPHIC_TRIP_POINT_MASK;
/* Low Temp Threshold (LTT) */
reg16 |= pch_get_ltt_value();
write16((uint16_t *)thermalbar_pm, reg16);
} }