soc/intel/common/thermal: Use `clrsetbits32()` for setting LTT
This patch uses `clrsetbits32` helper function to set thermal device Low Temp Threshold (LTT) value. BUG=b:193774296 TEST=Able to build and boot hatch and adlrvp with this change. Change-Id: I51fea7bd2146ea29ef476218c006f7350b32c006 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59310 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -40,7 +40,6 @@ static uint32_t pch_get_ltt_value(void)
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/* Enable thermal sensor power management */
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void pch_thermal_configuration(void)
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{
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uint16_t reg16;
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uintptr_t thermalbar;
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uintptr_t thermalbar_pm;
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const struct device *dev;
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@ -65,9 +64,5 @@ void pch_thermal_configuration(void)
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thermalbar_pm = thermalbar + THERMAL_SENSOR_POWER_MANAGEMENT;
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/* Set Low Temp Threshold (LTT) at TSPM offset 0x1c[8:0] */
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reg16 = read16((uint16_t *)thermalbar_pm);
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reg16 &= ~CATASTROPHIC_TRIP_POINT_MASK;
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/* Low Temp Threshold (LTT) */
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reg16 |= pch_get_ltt_value();
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write16((uint16_t *)thermalbar_pm, reg16);
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clrsetbits32((void *)thermalbar_pm, CATASTROPHIC_TRIP_POINT_MASK, pch_get_ltt_value());
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}
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