diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index e850fd1ae6..aa7711bf5c 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -712,7 +712,6 @@ static void haswell_init(struct device *cpu)
 
 /* MP initialization support. */
 static const void *microcode_patch;
-static int ht_disabled;
 
 static void pre_mp_init(void)
 {
@@ -740,8 +739,6 @@ static int get_cpu_count(void)
 	printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n",
 	       num_cores, num_threads);
 
-	ht_disabled = num_threads == num_cores;
-
 	return num_threads;
 }
 
@@ -752,14 +749,6 @@ static void get_microcode_info(const void **microcode, int *parallel)
 	*parallel = 1;
 }
 
-static int adjust_apic_id(int index, int apic_id)
-{
-	if (ht_disabled)
-		return 2 * index;
-	else
-		return index;
-}
-
 static void per_cpu_smm_trigger(void)
 {
 	/* Relocate the SMM handler. */
@@ -784,7 +773,6 @@ static const struct mp_ops mp_ops = {
 	.get_cpu_count = get_cpu_count,
 	.get_smm_info = smm_info,
 	.get_microcode_info = get_microcode_info,
-	.adjust_cpu_apic_entry = adjust_apic_id,
 	.pre_mp_smm_init = smm_initialize,
 	.per_cpu_smm_trigger = per_cpu_smm_trigger,
 	.relocation_handler = smm_relocation_handler,
diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c
index 4eb9519c7c..046aa60ec7 100644
--- a/src/cpu/x86/mp_init.c
+++ b/src/cpu/x86/mp_init.c
@@ -82,9 +82,6 @@ struct mp_params {
 	int num_cpus; /* Total cpus include BSP */
 	int parallel_microcode_load;
 	const void *microcode_pointer;
-	/* adjust_apic_id() is called for every potential APIC id in the
-	 * system up from 0 to CONFIG_MAX_CPUS. Return adjusted apic_id. */
-	int (*adjust_apic_id)(int index, int apic_id);
 	/* Flight plan  for APs and BSP. */
 	struct mp_flight_record *flight_plan;
 	int num_records;
@@ -133,12 +130,19 @@ static struct mp_flight_plan mp_info;
 
 struct cpu_map {
 	struct device *dev;
-	int apic_id;
+	/* Keep track of default apic ids for SMM. */
+	int default_apic_id;
 };
 
 /* Keep track of APIC and device structure for each CPU. */
 static struct cpu_map cpus[CONFIG_MAX_CPUS];
 
+static inline void add_cpu_map_entry(const struct cpu_info *info)
+{
+	cpus[info->index].dev = info->cpu;
+	cpus[info->index].default_apic_id = cpuid_ebx(1) >> 24;
+}
+
 inline void barrier_wait(atomic_t *b)
 {
 	while (atomic_read(b) == 0)
@@ -218,7 +222,6 @@ static void park_this_cpu(void)
 static void asmlinkage ap_init(unsigned int cpu)
 {
 	struct cpu_info *info;
-	int apic_id;
 
 	/* Ensure the local APIC is enabled */
 	enable_lapic();
@@ -226,13 +229,15 @@ static void asmlinkage ap_init(unsigned int cpu)
 	info = cpu_info();
 	info->index = cpu;
 	info->cpu = cpus[cpu].dev;
+
+	add_cpu_map_entry(info);
 	thread_init_cpu_info_non_bsp(info);
 
-	apic_id = lapicid();
-	info->cpu->path.apic.apic_id = apic_id;
-	cpus[cpu].apic_id = apic_id;
+	/* Fix up APIC id with reality. */
+	info->cpu->path.apic.apic_id = lapicid();
 
-	printk(BIOS_INFO, "AP: slot %d apic_id %x.\n", cpu, apic_id);
+	printk(BIOS_INFO, "AP: slot %d apic_id %x.\n", cpu,
+		info->cpu->path.apic.apic_id);
 
 	/* Walk the flight plan */
 	ap_do_flight_plan();
@@ -399,16 +404,13 @@ static int allocate_cpu_devices(struct bus *cpu_bus, struct mp_params *p)
 	for (i = 1; i < max_cpus; i++) {
 		struct device_path cpu_path;
 		struct device *new;
-		int apic_id;
 
 		/* Build the CPU device path */
 		cpu_path.type = DEVICE_PATH_APIC;
 
-		/* Assuming linear APIC space allocation. */
-		apic_id = info->cpu->path.apic.apic_id + i;
-		if (p->adjust_apic_id != NULL)
-			apic_id = p->adjust_apic_id(i, apic_id);
-		cpu_path.apic.apic_id = apic_id;
+		/* Assuming linear APIC space allocation. AP will set its own
+		   APIC id in the ap_init() path above. */
+		cpu_path.apic.apic_id = info->cpu->path.apic.apic_id + i;
 
 		/* Allocate the new CPU device structure */
 		new = alloc_find_dev(cpu_bus, &cpu_path);
@@ -583,8 +585,7 @@ static void init_bsp(struct bus *cpu_bus)
 		printk(BIOS_CRIT, "BSP index(%d) != 0!\n", info->index);
 
 	/* Track BSP in cpu_map structures. */
-	cpus[info->index].dev = info->cpu;
-	cpus[info->index].apic_id = cpu_path.apic.apic_id;
+	add_cpu_map_entry(info);
 }
 
 /*
@@ -668,7 +669,7 @@ static int mp_get_apic_id(int cpu_slot)
 	if (cpu_slot >= CONFIG_MAX_CPUS || cpu_slot < 0)
 		return -1;
 
-	return cpus[cpu_slot].apic_id;
+	return cpus[cpu_slot].default_apic_id;
 }
 
 void smm_initiate_relocation_parallel(void)
@@ -1015,7 +1016,6 @@ int mp_init_with_smm(struct bus *cpu_bus, const struct mp_ops *mp_ops)
 	if (mp_state.ops.get_microcode_info != NULL)
 		mp_state.ops.get_microcode_info(&mp_params.microcode_pointer,
 			&mp_params.parallel_microcode_load);
-	mp_params.adjust_apic_id = mp_state.ops.adjust_cpu_apic_entry;
 	mp_params.flight_plan = &mp_steps[0];
 	mp_params.num_records = ARRAY_SIZE(mp_steps);
 
diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h
index 0671b62551..f6afc84f35 100644
--- a/src/include/cpu/x86/mp.h
+++ b/src/include/cpu/x86/mp.h
@@ -57,14 +57,6 @@ struct mp_ops {
 	 * can load the microcode in parallel.
 	 */
 	void (*get_microcode_info)(const void **microcode, int *parallel);
-	/*
-	 * Optionally provide a function which adjusts the APIC id
-	 * map to CPU number. By default the CPU number and APIC id
-	 * are 1:1. To change the APIC id for a given CPU return the
-	 * new APIC id. It's called for each CPU as indicated by
-	 * get_cpu_count().
-	 */
-	int (*adjust_cpu_apic_entry)(int cpu, int cur_apic_id);
 	/*
 	 * Optionally adjust SMM handler parameters to override the default
 	 * values.  The is_perm variable indicates if the parameters to adjust
diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c
index 94c3f2b39e..a3844047c4 100644
--- a/src/soc/intel/baytrail/cpu.c
+++ b/src/soc/intel/baytrail/cpu.c
@@ -151,12 +151,6 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
 	*smm_save_state_size = sizeof(em64t100_smm_state_save_area_t);
 }
 
-/* The APIC id space on Bay Trail is sparse. Each id is separated by 2. */
-static int adjust_apic_id(int index, int apic_id)
-{
-	return 2 * index;
-}
-
 static void get_microcode_info(const void **microcode, int *parallel)
 {
 	const struct pattrs *pattrs = pattrs_get();
@@ -199,7 +193,6 @@ static const struct mp_ops mp_ops = {
 	.get_cpu_count = get_cpu_count,
 	.get_smm_info = get_smm_info,
 	.get_microcode_info = get_microcode_info,
-	.adjust_cpu_apic_entry = adjust_apic_id,
 	.pre_mp_smm_init = southcluster_smm_clear_state,
 	.per_cpu_smm_trigger = per_cpu_smm_trigger,
 	.relocation_handler = relocation_handler,
diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c
index 96c823a537..a2bd180da5 100644
--- a/src/soc/intel/braswell/cpu.c
+++ b/src/soc/intel/braswell/cpu.c
@@ -161,12 +161,6 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
 	*smm_save_state_size = sizeof(em64t100_smm_state_save_area_t);
 }
 
-/* The APIC id space on Bay Trail is sparse. Each id is separated by 2. */
-static int adjust_apic_id(int index, int apic_id)
-{
-	return 2 * index;
-}
-
 static void get_microcode_info(const void **microcode, int *parallel)
 {
 	const struct pattrs *pattrs = pattrs_get();
@@ -215,7 +209,6 @@ static const struct mp_ops mp_ops = {
 	.get_cpu_count = get_cpu_count,
 	.get_smm_info = get_smm_info,
 	.get_microcode_info = get_microcode_info,
-	.adjust_cpu_apic_entry = adjust_apic_id,
 	.pre_mp_smm_init = southcluster_smm_clear_state,
 	.per_cpu_smm_trigger = per_cpu_smm_trigger,
 	.relocation_handler = relocation_handler,
diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c
index b4db21b6a2..7b56db17fc 100644
--- a/src/soc/intel/broadwell/cpu.c
+++ b/src/soc/intel/broadwell/cpu.c
@@ -605,7 +605,6 @@ static void cpu_core_init(device_t cpu)
 
 /* MP initialization support. */
 static const void *microcode_patch;
-static int ht_disabled;
 
 static void pre_mp_init(void)
 {
@@ -630,8 +629,6 @@ static int get_cpu_count(void)
 	printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n",
 	       num_cores, num_threads);
 
-	ht_disabled = num_threads == num_cores;
-
 	return num_threads;
 }
 
@@ -642,14 +639,6 @@ static void get_microcode_info(const void **microcode, int *parallel)
 	*parallel = 1;
 }
 
-static int adjust_apic_id(int index, int apic_id)
-{
-	if (ht_disabled)
-		return 2 * index;
-	else
-		return index;
-}
-
 static void per_cpu_smm_trigger(void)
 {
 	/* Relocate the SMM handler. */
@@ -677,7 +666,6 @@ static const struct mp_ops mp_ops = {
 	.get_cpu_count = get_cpu_count,
 	.get_smm_info = smm_info,
 	.get_microcode_info = get_microcode_info,
-	.adjust_cpu_apic_entry = adjust_apic_id,
 	.pre_mp_smm_init = smm_initialize,
 	.per_cpu_smm_trigger = per_cpu_smm_trigger,
 	.relocation_handler = smm_relocation_handler,
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c
index 2faadfd492..4e065778fa 100644
--- a/src/soc/intel/cannonlake/cpu.c
+++ b/src/soc/intel/cannonlake/cpu.c
@@ -200,16 +200,6 @@ void soc_core_init(device_t cpu)
 
 }
 
-static int adjust_apic_id(int index, int apic_id)
-{
-	unsigned int num_cores, num_threads;
-
-	if (cpu_read_topology(&num_cores, &num_threads))
-		return 2 * index;
-	else
-		return index;
-}
-
 static void post_mp_init(void)
 {
 	/* Set Max Ratio */
@@ -225,7 +215,6 @@ static const struct mp_ops mp_ops = {
 	.pre_mp_init = soc_fsp_load,
 	.get_cpu_count = get_cpu_count,
 	.get_microcode_info = get_microcode_info,
-	.adjust_cpu_apic_entry = adjust_apic_id,
 	.post_mp_init = post_mp_init,
 };
 
diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c
index 742b2ef794..c3879e1f95 100644
--- a/src/soc/intel/fsp_baytrail/cpu.c
+++ b/src/soc/intel/fsp_baytrail/cpu.c
@@ -122,12 +122,6 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
 	*smm_save_state_size = sizeof(em64t100_smm_state_save_area_t);
 }
 
-/* The APIC id space on Bay Trail is sparse. Each id is separated by 2. */
-static int adjust_apic_id(int index, int apic_id)
-{
-	return 2 * index;
-}
-
 static void get_microcode_info(const void **microcode, int *parallel)
 {
 	const struct pattrs *pattrs = pattrs_get();
@@ -165,7 +159,6 @@ static const struct mp_ops mp_ops = {
 	.get_cpu_count = get_cpu_count,
 	.get_smm_info = get_smm_info,
 	.get_microcode_info = get_microcode_info,
-	.adjust_cpu_apic_entry = adjust_apic_id,
 	.pre_mp_smm_init = southcluster_smm_clear_state,
 	.relocation_handler = relocation_handler,
 	.post_mp_init = enable_smis,
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 0ad5dc9a72..1e12c6509f 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -421,16 +421,6 @@ void soc_core_init(device_t cpu)
 	prmrr_core_configure();
 }
 
-static int adjust_apic_id(int index, int apic_id)
-{
-	unsigned int num_cores, num_threads;
-
-	if (cpu_read_topology(&num_cores, &num_threads))
-		return 2 * index;
-	else
-		return index;
-}
-
 static void per_cpu_smm_trigger(void)
 {
 	/* Relocate the SMM handler. */
@@ -466,7 +456,6 @@ static const struct mp_ops mp_ops = {
 	.get_cpu_count = get_cpu_count,
 	.get_smm_info = smm_info,
 	.get_microcode_info = get_microcode_info,
-	.adjust_cpu_apic_entry = adjust_apic_id,
 	.pre_mp_smm_init = smm_initialize,
 	.per_cpu_smm_trigger = per_cpu_smm_trigger,
 	.relocation_handler = smm_relocation_handler,