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Fix socket LGA775 

Models 6ex and 6fx select UDELAY_LAPIC so cannot select
contradicting UDELAY_TSC here.

Model 1067x requires speedstep.

Change-Id: I69d3ec8085912dfbe5fe31c81fa0a437228fa48f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/2525
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2013-02-26 13:49:56 +02:00 committed by Marc Jones
parent e988b515f1
commit 5a22b14d47
2 changed files with 1 additions and 1 deletions
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1
src/cpu/intel/socket_LGA775/Kconfig
View File

@ -14,7 +14,6 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
select CPU_INTEL_MODEL_1067X select CPU_INTEL_MODEL_1067X
select MMX select MMX
select SSE select SSE
select UDELAY_TSC
select SIPI_VECTOR_IN_ROM select SIPI_VECTOR_IN_ROM
config DCACHE_RAM_SIZE config DCACHE_RAM_SIZE

1
src/cpu/intel/socket_LGA775/Makefile.inc
View File

@ -13,5 +13,6 @@ subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm subdirs-y += ../../x86/smm
subdirs-y += ../microcode subdirs-y += ../microcode
subdirs-y += ../hyperthreading subdirs-y += ../hyperthreading
subdirs-y += ../speedstep
cpu_incs-$(CONFIG_CACHE_AS_RAM) += $(src)/cpu/intel/car/cache_as_ram_ht.inc cpu_incs-$(CONFIG_CACHE_AS_RAM) += $(src)/cpu/intel/car/cache_as_ram_ht.inc