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mb/google/zork: update USB 2.0 controller Lane Parameter for dirinboz 

From AMD USB phy specialist recommended that for DB port2 (type-A), port3 (type-C C1)
the most effective corrections for the depressed eye are:
tx_rise_tune=0x0
tx_pre_emp_amp_tune=0x3
tx_fsls_tune = 0x3

BUG=b:165209698
BRANCH=zork
TEST=1. emerge-zork coreboot
     2. pass USB 2.0 SI eye diagram verification

Change-Id: I80afd6bf1257b9a72d0d7651b48d243ebaf5de2f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
This commit is contained in:
Kevin Chiu 2021-01-22 14:33:32 +08:00 committed by Patrick Georgi
parent cbde6410a0
commit 5a27b75642
1 changed files with 5 additions and 5 deletions
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10
src/mainboard/google/zork/variants/dirinboz/overridetree.cb
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@ -21,7 +21,7 @@ chip soc/amd/picasso
register "telemetry_vddcr_soc_offset" = "167" register "telemetry_vddcr_soc_offset" = "167"
# End : OPN Performance Configuration # End : OPN Performance Configuration
# USB 2.0 strength # USB 2.0 strength - MB type-C C0
register "usb_2_port_tune_params[0]" = "{ register "usb_2_port_tune_params[0]" = "{
.com_pds_tune = 0x07, .com_pds_tune = 0x07,
.sq_rx_tune = 0x3, .sq_rx_tune = 0x3,
@ -34,27 +34,27 @@ chip soc/amd/picasso
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"
# USB 2.0 strength # USB 2.0 strength - DB type-A
register "usb_2_port_tune_params[2]" = "{ register "usb_2_port_tune_params[2]" = "{
.com_pds_tune = 0x07, .com_pds_tune = 0x07,
.sq_rx_tune = 0x3, .sq_rx_tune = 0x3,
.tx_fsls_tune = 0x3, .tx_fsls_tune = 0x3,
.tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x0,
.tx_vref_tune = 0xe, .tx_vref_tune = 0xe,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"
# USB 2.0 strength # USB 2.0 strength - DB type-C C1
register "usb_2_port_tune_params[3]" = "{ register "usb_2_port_tune_params[3]" = "{
.com_pds_tune = 0x07, .com_pds_tune = 0x07,
.sq_rx_tune = 0x3, .sq_rx_tune = 0x3,
.tx_fsls_tune = 0x3, .tx_fsls_tune = 0x3,
.tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x0,
.tx_vref_tune = 0xe, .tx_vref_tune = 0xe,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,