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soc/intel/cannonlake: Make use of Intel SPI common block 

TEST=Build and boot RVP

Change-Id: I5ff9867f08e43016a797b1b3719053df0c382174
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Subrata Banik 2017-11-07 18:06:36 +05:30 committed by Aaron Durbin
parent cca50852fe
commit 5a283ef65c
3 changed files with 2 additions and 56 deletions
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1
src/soc/intel/cannonlake/Kconfig
View File

@ -65,6 +65,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_SMBUS
select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
select SOC_INTEL_COMMON_BLOCK_SPI
select SOC_INTEL_COMMON_BLOCK_TIMER
select SOC_INTEL_COMMON_BLOCK_UART
select SOC_INTEL_COMMON_SPI_FLASH_PROTECT

2
src/soc/intel/cannonlake/Makefile.inc
View File

@ -54,13 +54,11 @@ ramstage-y += sd.c
smm-y += gpio.c
smm-y += pmutil.c
smm-y += smihandler.c
smm-$(CONFIG_SPI_FLASH_SMM) += spi.c
smm-$(CONFIG_UART_DEBUG) += uart.c
smm-$(CONFIG_UART_DEBUG) += uart_pch.c
postcar-y += memmap.c
postcar-y += pmutil.c
postcar-y += spi.c
postcar-$(CONFIG_UART_DEBUG) += uart.c
verstage-y += gspi.c

55
src/soc/intel/cannonlake/spi.c
View File

@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright 2017 Google Inc.
* Copyright 2017 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -14,18 +15,8 @@
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <device/spi.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/gspi.h>
#include <intelblocks/spi.h>
#include <soc/ramstage.h>
#include <soc/pci_devs.h>
#include <spi-generic.h>
int spi_soc_devfn_to_bus(unsigned int devfn)
{
@ -56,47 +47,3 @@ int spi_soc_bus_to_devfn(unsigned int bus)
}
return -1;
}
const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
{ .ctrlr = &fast_spi_flash_ctrlr, .bus_start = 0, .bus_end = 0 },
#if !ENV_SMM
{ .ctrlr = &gspi_ctrlr, .bus_start = 1,
.bus_end = 1 + (CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX - 1)},
#endif
};
const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
#if ENV_RAMSTAGE
static int spi_dev_to_bus(struct device *dev)
{
return spi_soc_devfn_to_bus(dev->path.pci.devfn);
}
static struct spi_bus_operations spi_bus_ops = {
.dev_to_bus = &spi_dev_to_bus,
};
static struct device_operations spi_dev_ops = {
.read_resources = &pci_dev_read_resources,
.set_resources = &pci_dev_set_resources,
.enable_resources = &pci_dev_enable_resources,
.scan_bus = &scan_generic_bus,
.ops_spi_bus = &spi_bus_ops,
};
static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_INTEL_CNL_HWSEQ_SPI,
PCI_DEVICE_ID_INTEL_CNL_SPI0,
PCI_DEVICE_ID_INTEL_CNL_SPI1,
PCI_DEVICE_ID_INTEL_CNL_SPI2,
0
};
static const struct pci_driver pch_spi __pci_driver = {
.ops = &spi_dev_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.devices = pci_device_ids,
};
#endif