GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/intel/tglrvp: Enable HECI interface 

This is to enable Intel ME communication interface HECI1 by
devicetree for PAVP with CSE Lite.
PAVP feature is enabled with CSE Lite SKU for Chrome and HECI1 interface
is required between kernel and CSE Lite.

BUG=None
TEST=Build and boot tglrvp. Run lspci and check pcie device
     00:16.0 Communication controller: Intel Corporation Device a0e0

Change-Id: I23117fa96503942e6a72765dd3fd1cc762e3f705
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Jamie Ryu 2020-06-12 02:47:14 -07:00 committed by Patrick Georgi
parent 388e551dc3
commit 5a401ae262
2 changed files with 6 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
View File

@ -12,6 +12,9 @@ chip soc/intel/tigerlake
register "pmc_gpe0_dw1" = "GPP_D"
register "pmc_gpe0_dw2" = "GPP_E"
# Enable heci1 communication
register "HeciEnabled" = "1"
# FSP configuration
register "SaGv" = "SaGv_Enabled"
register "SmbusEnable" = "1"

3
src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
View File

@ -12,6 +12,9 @@ chip soc/intel/tigerlake
register "pmc_gpe0_dw1" = "GPP_D"
register "pmc_gpe0_dw2" = "GPP_E"
# Enable heci1 communication
register "HeciEnabled" = "1"
# FSP configuration
register "SaGv" = "SaGv_Disabled"
register "SmbusEnable" = "1"