Port persimmon r6573 to e350m1: VGA, PCI MMIO and SB800 legacy
1) Use D18F1xF4 VGA Enable to simplify legacy video I/O support. 2) Extend PCI MMIO limit from dfffffff to fecfffff. 3) Add AMD recommended non-posted mapping for SB800 legacy devices. Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6622 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -85,38 +85,39 @@ agesawrapper_amdinitcpuio (
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PCI_ADDR PciAddress;
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PCI_ADDR PciAddress;
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AMD_CONFIG_PARAMS StdHeader;
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AMD_CONFIG_PARAMS StdHeader;
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/* Enable MMIO on AMD CPU Address Map Controller */
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/* Enable legacy video routing: D18F1xF4 VGA Enable */
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
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/* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */
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PciData = 1;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* The platform BIOS needs to ensure the memory ranges of SB800 legacy
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* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
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* set to non-posted regions.
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*/
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
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PciData = 0x00000B00;
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PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
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PciData |= 1 << 7; // set NP (non-posted) bit
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
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PciData = 0x00000A03;
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PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* Set TOM-DFFFFFFF to Node0 Link0. */
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/* Map the remaining PCI hole as posted MMIO */
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
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PciData = 0x00DFFF00;
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PciData = 0x00FECF00; // last address before non-posted range
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
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LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
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MsrReg = (MsrReg >> 8) | 3;
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MsrReg = (MsrReg >> 8) | 3;
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
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PciData = (UINT32)MsrReg;
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PciData = (UINT32)MsrReg;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xBC);
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/* Send all IO (0000-FFFF) to southbridge. */
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PciData = 0x00FFFF00 | 0x80;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xB8);
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PciData = (PCIE_BASE_ADDRESS >> 8) | 03;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* Start to set PCIIO 0000-FFFF to Node0 Link0 with ISA&VGA set. */
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
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PciData = 0x0000F000;
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PciData = 0x0000F000;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
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PciData = 0x00000013;
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PciData = 0x00000003;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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Status = AGESA_SUCCESS;
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Status = AGESA_SUCCESS;
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return (UINT32)Status;
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return (UINT32)Status;
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