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coreboot-kgpe-d16
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match against all steppings of a CPU model, because these are _model_ drivers. 

(trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3455 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2008-08-01 12:11:00 +00:00 committed by Stefan Reinauer
parent ac555b1c69
commit 5a522d4a42
3 changed files with 9 additions and 3 deletions
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3
src/cpu/intel/model_69x/model_69x_init.c
View File

@ -38,7 +38,8 @@ static struct device_operations cpu_dev_ops = {
.init = model_69x_init, .init = model_69x_init,
}; };
static struct cpu_device_id cpu_table[] = { static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_INTEL, 0x0695 }, /* Pentium M */ { X86_VENDOR_INTEL, 0x0690 }, /* Pentium M */
{ X86_VENDOR_INTEL, 0x0695 },
{ 0, 0 }, { 0, 0 },
}; };

1
src/cpu/intel/model_6dx/model_6dx_init.c
View File

@ -38,6 +38,7 @@ static struct device_operations cpu_dev_ops = {
.init = model_6dx_init, .init = model_6dx_init,
}; };
static struct cpu_device_id cpu_table[] = { static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_INTEL, 0x06D0 }, /* Pentium M on 90nm with 2MiB of L2 cache */
{ X86_VENDOR_INTEL, 0x06D6 }, /* Pentium M on 90nm with 2MiB of L2 cache */ { X86_VENDOR_INTEL, 0x06D6 }, /* Pentium M on 90nm with 2MiB of L2 cache */
{ 0, 0 }, { 0, 0 },
}; };

8
src/cpu/intel/model_6xx/model_6xx_init.c
View File

@ -44,17 +44,21 @@ static struct device_operations cpu_dev_ops = {
.init = model_6xx_init, .init = model_6xx_init,
}; };
static struct cpu_device_id cpu_table[] = { static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_INTEL, 0x0650 },
{ X86_VENDOR_INTEL, 0x0652 }, { X86_VENDOR_INTEL, 0x0652 },
{ X86_VENDOR_INTEL, 0x0665 }, /* Celeron (Mendocino) */ { X86_VENDOR_INTEL, 0x0660 }, /* Celeron (Mendocino) */
{ X86_VENDOR_INTEL, 0x0665 },
{ X86_VENDOR_INTEL, 0x0672 }, { X86_VENDOR_INTEL, 0x0672 },
{ X86_VENDOR_INTEL, 0x0673 }, { X86_VENDOR_INTEL, 0x0673 },
{ X86_VENDOR_INTEL, 0x0680 },
{ X86_VENDOR_INTEL, 0x0681 }, { X86_VENDOR_INTEL, 0x0681 },
{ X86_VENDOR_INTEL, 0x0683 }, { X86_VENDOR_INTEL, 0x0683 },
{ X86_VENDOR_INTEL, 0x0686 }, { X86_VENDOR_INTEL, 0x0686 },
{ X86_VENDOR_INTEL, 0x06A0 }, { X86_VENDOR_INTEL, 0x06A0 },
{ X86_VENDOR_INTEL, 0x06A1 }, { X86_VENDOR_INTEL, 0x06A1 },
{ X86_VENDOR_INTEL, 0x06A4 }, { X86_VENDOR_INTEL, 0x06A4 },
{ X86_VENDOR_INTEL, 0x06B4 }, /* Mobile Celeron FCBGA */ { X86_VENDOR_INTEL, 0x06B0 }, /* Mobile Celeron FCBGA */
{ X86_VENDOR_INTEL, 0x06B4 },
{ 0, 0 }, { 0, 0 },
}; };