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soc/intel/baytrail,braswell: Do resource transition 

Change-Id: Ia44be7d63b0e6e16a49695d430715a7e5785d530
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55925
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2021-06-24 20:49:05 +03:00
parent 1cc775ef9d
commit 5a55a455cd
4 changed files with 21 additions and 33 deletions
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2
src/soc/intel/baytrail/northcluster.c
View File

@ -77,7 +77,7 @@ static void nc_read_resources(struct device *dev)
/* PCIe memory-mapped config space access - 256 MiB. */
mmconf = iosf_bunit_read(BUNIT_MMCONF_REG) & ~((1 << 28) - 1);
mmio_resource_kb(dev, BUNIT_MMCONF_REG, RES_IN_KiB(mmconf), 256 * 1024);
mmio_range(dev, BUNIT_MMCONF_REG, mmconf, CONFIG_ECAM_MMCONF_BUS_NUMBER * MiB);
/* 0 -> 0xa0000 */
base_k = RES_IN_KiB(0);

22
src/soc/intel/baytrail/southcluster.c
View File

@ -23,22 +23,16 @@
#include "chip.h"
#include <acpi/acpigen.h>
static inline void add_mmio_resource(struct device *dev, int i, unsigned long addr,
unsigned long size)
{
mmio_resource_kb(dev, i, addr >> 10, size >> 10);
}
static void sc_add_mmio_resources(struct device *dev)
{
add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE);
add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE);
add_mmio_resource(dev, IOBASE, IO_BASE_ADDRESS, IO_BASE_SIZE);
add_mmio_resource(dev, IBASE, ILB_BASE_ADDRESS, ILB_BASE_SIZE);
add_mmio_resource(dev, SBASE, SPI_BASE_ADDRESS, SPI_BASE_SIZE);
add_mmio_resource(dev, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE);
add_mmio_resource(dev, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE);
add_mmio_resource(dev, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE);
mmio_range(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE);
mmio_range(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE);
mmio_range(dev, IOBASE, IO_BASE_ADDRESS, IO_BASE_SIZE);
mmio_range(dev, IBASE, ILB_BASE_ADDRESS, ILB_BASE_SIZE);
mmio_range(dev, SBASE, SPI_BASE_ADDRESS, SPI_BASE_SIZE);
mmio_range(dev, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE);
mmio_range(dev, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE);
mmio_range(dev, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE);
}
/* Default IO range claimed by the LPC device. The upper bound is exclusive. */

2
src/soc/intel/braswell/northcluster.c
View File

@ -99,7 +99,7 @@ static void nc_read_resources(struct device *dev)
/* PCIe memory-mapped config space access - 256 MiB. */
mmconf = iosf_bunit_read(BUNIT_MMCONF_REG) & ~((1 << 28) - 1);
mmio_resource_kb(dev, BUNIT_MMCONF_REG, RES_IN_KiB(mmconf), 256 * 1024);
mmio_range(dev, BUNIT_MMCONF_REG, mmconf, CONFIG_ECAM_MMCONF_BUS_NUMBER * MiB);
/* 0 -> 0xa0000 */
base_k = RES_IN_KiB(0);

28
src/soc/intel/braswell/southcluster.c
View File

@ -45,26 +45,20 @@ static void sc_set_serial_irqs_mode(struct device *dev, enum serirq_mode mode)
}
}
static inline void add_mmio_resource(struct device *dev, int i, unsigned long addr,
unsigned long size)
{
mmio_resource_kb(dev, i, addr >> 10, size >> 10);
}
static void sc_add_mmio_resources(struct device *dev)
{
add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE);
add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE);
add_mmio_resource(dev, IOBASE, IO_BASE_ADDRESS, IO_BASE_SIZE);
add_mmio_resource(dev, IBASE, ILB_BASE_ADDRESS, ILB_BASE_SIZE);
add_mmio_resource(dev, SBASE, SPI_BASE_ADDRESS, SPI_BASE_SIZE);
add_mmio_resource(dev, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE);
add_mmio_resource(dev, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE);
add_mmio_resource(dev, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE);
add_mmio_resource(dev, 0xfff, 0xffffffff - (CONFIG_COREBOOT_ROMSIZE_KB * KiB) + 1,
(CONFIG_COREBOOT_ROMSIZE_KB * KiB)); /* BIOS ROM */
mmio_range(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE);
mmio_range(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE);
mmio_range(dev, IOBASE, IO_BASE_ADDRESS, IO_BASE_SIZE);
mmio_range(dev, IBASE, ILB_BASE_ADDRESS, ILB_BASE_SIZE);
mmio_range(dev, SBASE, SPI_BASE_ADDRESS, SPI_BASE_SIZE);
mmio_range(dev, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE);
mmio_range(dev, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE);
mmio_range(dev, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE);
mmio_range(dev, 0xfff, 0xffffffff - (CONFIG_COREBOOT_ROMSIZE_KB * KiB) + 1,
CONFIG_COREBOOT_ROMSIZE_KB * KiB); /* BIOS ROM */
add_mmio_resource(dev, 0xfec, IO_APIC_ADDR, 0x00001000); /* IOAPIC */
mmio_range(dev, 0xfec, IO_APIC_ADDR, 0x00001000); /* IOAPIC */
}
/* Default IO range claimed by the LPC device. The upper bound is exclusive. */