Intel cpus: copy model_6ex CAR code
Copy model_6ex CAR as car/cache_as_ram_ht.inc to be extended with hyper-threading CPU support. Change-Id: I09619363e714b1ebf813932b0b22123c1d89010e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/606 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Kyösti Mälkki
Patrick Georgi
parent
d842f1fe24
commit
5a660ca229
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
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* Copyright (C) 2007-2008 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <cpu/x86/stack.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/post_code.h>
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#define CPU_MAXPHYADDR 36
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#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1)
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#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
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#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
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/* Save the BIST result. */
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movl %eax, %ebp
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cache_as_ram:
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post_code(0x20)
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/* Send INIT IPI to all excluding ourself. */
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movl $0x000C4500, %eax
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movl $0xFEE00300, %esi
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movl %eax, (%esi)
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/* Zero out all fixed range and variable range MTRRs. */
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movl $mtrr_table, %esi
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movl $((mtrr_table_end - mtrr_table) / 2), %edi
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xorl %eax, %eax
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xorl %edx, %edx
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clear_mtrrs:
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movw (%esi), %bx
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movzx %bx, %ecx
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wrmsr
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add $2, %esi
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dec %edi
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jnz clear_mtrrs
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/* Configure the default memory type to uncacheable. */
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movl $MTRRdefType_MSR, %ecx
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rdmsr
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andl $(~0x00000cff), %eax
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wrmsr
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/* Set Cache-as-RAM base address. */
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movl $(MTRRphysBase_MSR(0)), %ecx
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movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
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xorl %edx, %edx
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wrmsr
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/* Set Cache-as-RAM mask. */
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movl $(MTRRphysMask_MSR(0)), %ecx
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movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
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movl $CPU_PHYSMASK_HI, %edx
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wrmsr
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/* Enable MTRR. */
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movl $MTRRdefType_MSR, %ecx
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rdmsr
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orl $MTRRdefTypeEn, %eax
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wrmsr
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/* Enable L2 cache. */
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movl $0x11e, %ecx
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rdmsr
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orl $(1 << 8), %eax
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wrmsr
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/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
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movl %cr0, %eax
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andl $(~((1 << 30) | (1 << 29))), %eax
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invd
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movl %eax, %cr0
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/* Clear the cache memory reagion. */
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movl $CACHE_AS_RAM_BASE, %esi
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movl %esi, %edi
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movl $(CACHE_AS_RAM_SIZE / 4), %ecx
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// movl $0x23322332, %eax
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xorl %eax, %eax
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rep stosl
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/* Enable Cache-as-RAM mode by disabling cache. */
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movl %cr0, %eax
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orl $(1 << 30), %eax
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movl %eax, %cr0
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#if CONFIG_XIP_ROM_SIZE
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/* Enable cache for our code in Flash because we do XIP here */
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movl $MTRRphysBase_MSR(1), %ecx
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xorl %edx, %edx
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/*
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* IMPORTANT: The following calculation _must_ be done at runtime. See
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* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
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*/
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movl $copy_and_run, %eax
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andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
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orl $MTRR_TYPE_WRBACK, %eax
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wrmsr
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movl $MTRRphysMask_MSR(1), %ecx
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movl $CPU_PHYSMASK_HI, %edx
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movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
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wrmsr
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#endif /* CONFIG_XIP_ROM_SIZE */
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/* Enable cache. */
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movl %cr0, %eax
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andl $(~((1 << 30) | (1 << 29))), %eax
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movl %eax, %cr0
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/* Set up the stack pointer. */
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#if CONFIG_USBDEBUG
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/* Leave some space for the struct ehci_debug_info. */
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movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax
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#else
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movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax
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#endif
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movl %eax, %esp
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/* Restore the BIST result. */
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movl %ebp, %eax
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movl %esp, %ebp
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pushl %eax
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post_code(0x23)
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/* Call romstage.c main function. */
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call main
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post_code(0x2f)
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post_code(0x30)
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/* Disable cache. */
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movl %cr0, %eax
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orl $(1 << 30), %eax
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movl %eax, %cr0
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post_code(0x31)
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/* Disable MTRR. */
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movl $MTRRdefType_MSR, %ecx
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rdmsr
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andl $(~MTRRdefTypeEn), %eax
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wrmsr
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post_code(0x31)
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invd
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#if 0
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xorl %eax, %eax
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xorl %edx, %edx
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movl $MTRRphysBase_MSR(0), %ecx
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wrmsr
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movl $MTRRphysMask_MSR(0), %ecx
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wrmsr
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movl $MTRRphysBase_MSR(1), %ecx
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wrmsr
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movl $MTRRphysMask_MSR(1), %ecx
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wrmsr
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#endif
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post_code(0x33)
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/* Enable cache. */
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movl %cr0, %eax
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andl $~((1 << 30) | (1 << 29)), %eax
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movl %eax, %cr0
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post_code(0x36)
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/* Disable cache. */
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movl %cr0, %eax
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orl $(1 << 30), %eax
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movl %eax, %cr0
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post_code(0x38)
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/* Enable Write Back and Speculative Reads for the first 1MB. */
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movl $MTRRphysBase_MSR(0), %ecx
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movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax
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xorl %edx, %edx
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wrmsr
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movl $MTRRphysMask_MSR(0), %ecx
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movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
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movl $CPU_PHYSMASK_HI, %edx
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wrmsr
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/* Enable caching and Speculative Reads for the last 4MB. */
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movl $MTRRphysBase_MSR(1), %ecx
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movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax
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xorl %edx, %edx
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wrmsr
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movl $MTRRphysMask_MSR(1), %ecx
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movl $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax
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movl $CPU_PHYSMASK_HI, %edx
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wrmsr
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post_code(0x39)
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/* And enable cache again after setting MTRRs. */
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movl %cr0, %eax
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andl $~((1 << 30) | (1 << 29)), %eax
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movl %eax, %cr0
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post_code(0x3a)
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/* Enable MTRR. */
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movl $MTRRdefType_MSR, %ecx
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rdmsr
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orl $MTRRdefTypeEn, %eax
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wrmsr
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post_code(0x3b)
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/* Invalidate the cache again. */
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invd
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post_code(0x3c)
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/* Clear boot_complete flag. */
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xorl %ebp, %ebp
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__main:
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post_code(POST_PREPARE_RAMSTAGE)
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cld /* Clear direction flag. */
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movl %ebp, %esi
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movl $ROMSTAGE_STACK, %esp
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movl %esp, %ebp
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pushl %esi
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call copy_and_run
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.Lhlt:
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post_code(POST_DEAD_CODE)
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hlt
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jmp .Lhlt
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mtrr_table:
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/* Fixed MTRRs */
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.word 0x250, 0x258, 0x259
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.word 0x268, 0x269, 0x26A
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.word 0x26B, 0x26C, 0x26D
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.word 0x26E, 0x26F
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/* Variable MTRRs */
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.word 0x200, 0x201, 0x202, 0x203
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.word 0x204, 0x205, 0x206, 0x207
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.word 0x208, 0x209, 0x20A, 0x20B
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.word 0x20C, 0x20D, 0x20E, 0x20F
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mtrr_table_end:
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