amdblocks/acpimmio: add common functions for AP entry

Move the stoneyridge implementation of get/set AP entry to the common
block.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I9c73940ffe5f735dcd844911361355c384f617b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>

src/soc/amd/common/block/acpimmio/biosram.c

@@ -15,6 +15,17 @@
 #include <amdblocks/acpimmio.h>
 #include <amdblocks/biosram.h>
 
+void *get_ap_entry_ptr(void)
+{
+	return (void *)biosram_read32(BIOSRAM_AP_ENTRY);
+}
+
+void set_ap_entry_ptr(void *entry)
+{
+	biosram_write32(BIOSRAM_AP_ENTRY, (uintptr_t)entry);
+}
+
+
 void backup_top_of_low_cacheable(uintptr_t ramtop)
 {
 	biosram_write32(BIOSRAM_CBMEM_TOP, ramtop);

src/soc/amd/common/block/include/amdblocks/biosram.h

@@ -17,10 +17,15 @@
 #include <stdint.h>
 
 /* BiosRam Ranges at 0xfed80500 or I/O 0xcd4/0xcd5 */
+#define BIOSRAM_AP_ENTRY		0xe8 /* 8 bytes */
 #define BIOSRAM_CBMEM_TOP		0xf0 /* 4 bytes */
 #define BIOSRAM_UMA_SIZE		0xf4 /* 4 bytes */
 #define BIOSRAM_UMA_BASE		0xf8 /* 8 bytes */
 
+/* Returns the bootblock C entry point for APs */
+void *get_ap_entry_ptr(void);
+/* Used by BSP to store the bootblock entry point for APs */
+void set_ap_entry_ptr(void *entry);
 /* Saves the UMA size returned by AGESA */
 void save_uma_size(uint32_t size);
 /* Saves the UMA base address returned by AGESA */

src/soc/amd/stoneyridge/Makefile.inc

@@ -48,7 +48,6 @@ bootblock-y += pmutil.c
 bootblock-y += reset.c
 bootblock-y += tsc_freq.c
 bootblock-y += southbridge.c
-bootblock-y += nb_util.c
 bootblock-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
 
 romstage-y += BiosCallOuts.c
@@ -65,7 +64,6 @@ romstage-y += memmap.c
 romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
 romstage-y += tsc_freq.c
 romstage-y += southbridge.c
-romstage-y += nb_util.c
 romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
 
 verstage-y += gpio.c
@@ -75,12 +73,10 @@ verstage-y += pmutil.c
 verstage-y += reset.c
 verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
 verstage-y += tsc_freq.c
-verstage-y += nb_util.c
 
 postcar-y += monotonic_timer.c
 postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c
 postcar-y += memmap.c
-postcar-y += nb_util.c
 postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c
 postcar-y += tsc_freq.c
 
@@ -107,14 +103,12 @@ ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
 ramstage-y += usb.c
 ramstage-y += tsc_freq.c
 ramstage-y += finalize.c
-ramstage-y += nb_util.c
 
 smm-y += monotonic_timer.c
 smm-y += smihandler.c
 smm-y += smi_util.c
 smm-y += tsc_freq.c
 smm-$(CONFIG_DEBUG_SMI) += uart.c
-smm-y += nb_util.c
 smm-y += gpio.c
 
 CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge

src/soc/amd/stoneyridge/bootblock/bootblock.c

@@ -24,9 +24,9 @@
 #include <bootblock_common.h>
 #include <amdblocks/agesawrapper.h>
 #include <amdblocks/agesawrapper_call.h>
+#include <amdblocks/biosram.h>
 #include <soc/pci_devs.h>
 #include <soc/cpu.h>
-#include <soc/northbridge.h>
 #include <soc/southbridge.h>
 #include <amdblocks/psp.h>
 #include <timestamp.h>

src/soc/amd/stoneyridge/include/soc/northbridge.h

@@ -40,8 +40,6 @@
 #define  NB_IOAPIC_SCRATCH0	0x3e
 #define  NB_IOAPIC_SCRATCH1	0x3f
 
-#define AP_SCRATCH_REG		NB_IOAPIC_SCRATCH0
-
 /* D1F1 - HDA Configuration Registers */
 #define HDA_DEV_CTRL_STATUS	0x60
 #define   HDA_NO_SNOOP_EN	BIT(11)
@@ -102,10 +100,6 @@
 void domain_enable_resources(struct device *dev);
 void domain_set_resources(struct device *dev);
 void fam15_finalize(void *chip_info);
-uint32_t nb_ioapic_read(unsigned int index);
-void nb_ioapic_write(unsigned int index, uint32_t value);
-void *get_ap_entry_ptr(void);
-void set_ap_entry_ptr(void *entry);
 void set_warm_reset_flag(void);
 int is_warm_reset(void);
 

src/soc/amd/stoneyridge/nb_util.c

@@ -1,40 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2018 Advanced Micro Devices
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <soc/northbridge.h>
-#include <soc/pci_devs.h>
-#include <device/pci_ops.h>
-
-uint32_t nb_ioapic_read(unsigned int index)
-{
-	pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index);
-	return pci_read_config32(SOC_GNB_DEV, NB_IOAPIC_DATA);
-}
-
-void nb_ioapic_write(unsigned int index, uint32_t value)
-{
-	pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index);
-	pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, value);
-}
-
-void *get_ap_entry_ptr(void)
-{
-	return (void *)nb_ioapic_read(AP_SCRATCH_REG);
-}
-
-void set_ap_entry_ptr(void *entry)
-{
-	nb_ioapic_write(AP_SCRATCH_REG, (uintptr_t)entry);
-}

src/soc/amd/stoneyridge/romstage.c

@@ -14,6 +14,7 @@
  * GNU General Public License for more details.
  */
 
+#include <amdblocks/biosram.h>
 #include <device/pci_ops.h>
 #include <arch/cpu.h>
 #include <arch/romstage.h>