amdblocks/acpimmio: add common functions for AP entry
Move the stoneyridge implementation of get/set AP entry to the common block. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I9c73940ffe5f735dcd844911361355c384f617b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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@ -15,6 +15,17 @@
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/biosram.h>
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void *get_ap_entry_ptr(void)
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{
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return (void *)biosram_read32(BIOSRAM_AP_ENTRY);
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}
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void set_ap_entry_ptr(void *entry)
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{
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biosram_write32(BIOSRAM_AP_ENTRY, (uintptr_t)entry);
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}
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void backup_top_of_low_cacheable(uintptr_t ramtop)
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{
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biosram_write32(BIOSRAM_CBMEM_TOP, ramtop);
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@ -17,10 +17,15 @@
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#include <stdint.h>
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/* BiosRam Ranges at 0xfed80500 or I/O 0xcd4/0xcd5 */
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#define BIOSRAM_AP_ENTRY 0xe8 /* 8 bytes */
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#define BIOSRAM_CBMEM_TOP 0xf0 /* 4 bytes */
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#define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */
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#define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */
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/* Returns the bootblock C entry point for APs */
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void *get_ap_entry_ptr(void);
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/* Used by BSP to store the bootblock entry point for APs */
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void set_ap_entry_ptr(void *entry);
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/* Saves the UMA size returned by AGESA */
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void save_uma_size(uint32_t size);
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/* Saves the UMA base address returned by AGESA */
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@ -48,7 +48,6 @@ bootblock-y += pmutil.c
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bootblock-y += reset.c
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bootblock-y += tsc_freq.c
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bootblock-y += southbridge.c
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bootblock-y += nb_util.c
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bootblock-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
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romstage-y += BiosCallOuts.c
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@ -65,7 +64,6 @@ romstage-y += memmap.c
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romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
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romstage-y += tsc_freq.c
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romstage-y += southbridge.c
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romstage-y += nb_util.c
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romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
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verstage-y += gpio.c
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@ -75,12 +73,10 @@ verstage-y += pmutil.c
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verstage-y += reset.c
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verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
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verstage-y += tsc_freq.c
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verstage-y += nb_util.c
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postcar-y += monotonic_timer.c
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postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c
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postcar-y += memmap.c
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postcar-y += nb_util.c
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postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c
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postcar-y += tsc_freq.c
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@ -107,14 +103,12 @@ ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
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ramstage-y += usb.c
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ramstage-y += tsc_freq.c
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ramstage-y += finalize.c
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ramstage-y += nb_util.c
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smm-y += monotonic_timer.c
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smm-y += smihandler.c
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smm-y += smi_util.c
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smm-y += tsc_freq.c
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smm-$(CONFIG_DEBUG_SMI) += uart.c
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smm-y += nb_util.c
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smm-y += gpio.c
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CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge
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@ -24,9 +24,9 @@
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#include <bootblock_common.h>
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#include <amdblocks/agesawrapper.h>
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#include <amdblocks/agesawrapper_call.h>
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#include <amdblocks/biosram.h>
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#include <soc/pci_devs.h>
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#include <soc/cpu.h>
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#include <soc/northbridge.h>
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#include <soc/southbridge.h>
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#include <amdblocks/psp.h>
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#include <timestamp.h>
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@ -40,8 +40,6 @@
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#define NB_IOAPIC_SCRATCH0 0x3e
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#define NB_IOAPIC_SCRATCH1 0x3f
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#define AP_SCRATCH_REG NB_IOAPIC_SCRATCH0
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/* D1F1 - HDA Configuration Registers */
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#define HDA_DEV_CTRL_STATUS 0x60
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#define HDA_NO_SNOOP_EN BIT(11)
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@ -102,10 +100,6 @@
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void domain_enable_resources(struct device *dev);
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void domain_set_resources(struct device *dev);
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void fam15_finalize(void *chip_info);
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uint32_t nb_ioapic_read(unsigned int index);
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void nb_ioapic_write(unsigned int index, uint32_t value);
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void *get_ap_entry_ptr(void);
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void set_ap_entry_ptr(void *entry);
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void set_warm_reset_flag(void);
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int is_warm_reset(void);
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@ -1,40 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Advanced Micro Devices
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <soc/northbridge.h>
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#include <soc/pci_devs.h>
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#include <device/pci_ops.h>
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uint32_t nb_ioapic_read(unsigned int index)
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{
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pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index);
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return pci_read_config32(SOC_GNB_DEV, NB_IOAPIC_DATA);
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}
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void nb_ioapic_write(unsigned int index, uint32_t value)
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{
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pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index);
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pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, value);
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}
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void *get_ap_entry_ptr(void)
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{
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return (void *)nb_ioapic_read(AP_SCRATCH_REG);
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}
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void set_ap_entry_ptr(void *entry)
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{
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nb_ioapic_write(AP_SCRATCH_REG, (uintptr_t)entry);
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}
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@ -14,6 +14,7 @@
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* GNU General Public License for more details.
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*/
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#include <amdblocks/biosram.h>
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#include <device/pci_ops.h>
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#include <arch/cpu.h>
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#include <arch/romstage.h>
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