x86: dynamic cbmem: fix acpi reservations
If a configuration was not using RELOCTABLE_RAMSTAGE, but it was using HAVE_ACPI_RESUME then the ACPI memory was not being marked as reserved to the OS. The reason is that memory is marked as reserved during write_coreboot_table(). These reservations were being added to cbmem after the call to write_coreboot_table(). In the non-dynamic cbmem case this sequence is fine because cbmem area is a fixed size and is already reserved. For the dynamic cbmem case that no longer holds by the nature of the dynamic cbmem. Change-Id: I9aa44205205bfef75a9e7d9f02cf5c93d7c457b2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2897 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -203,6 +203,22 @@ struct lb_memory *write_tables(void)
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}
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}
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#endif
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#endif
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post_code(0x9e);
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#if CONFIG_HAVE_ACPI_RESUME
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/* Only add CBMEM_ID_RESUME when the ramstage isn't relocatable. */
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#if !CONFIG_RELOCATABLE_RAMSTAGE
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/* Let's prepare the ACPI S3 Resume area now already, so we can rely on
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* it begin there during reboot time. We don't need the pointer, nor
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* the result right now. If it fails, ACPI resume will be disabled.
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*/
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cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE);
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#endif
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#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
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cbmem_add(CBMEM_ID_RESUME_SCRATCH, CONFIG_HIGH_SCRATCH_MEMORY_SIZE);
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#endif
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#endif
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#define MAX_COREBOOT_TABLE_SIZE (32 * 1024)
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#define MAX_COREBOOT_TABLE_SIZE (32 * 1024)
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post_code(0x9d);
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post_code(0x9d);
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@ -230,22 +246,6 @@ struct lb_memory *write_tables(void)
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rom_table_start, rom_table_end);
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rom_table_start, rom_table_end);
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}
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}
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post_code(0x9e);
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#if CONFIG_HAVE_ACPI_RESUME
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/* Only add CBMEM_ID_RESUME when the ramstage isn't relocatable. */
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#if !CONFIG_RELOCATABLE_RAMSTAGE
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/* Let's prepare the ACPI S3 Resume area now already, so we can rely on
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* it begin there during reboot time. We don't need the pointer, nor
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* the result right now. If it fails, ACPI resume will be disabled.
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*/
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cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE);
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#endif
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#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
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cbmem_add(CBMEM_ID_RESUME_SCRATCH, CONFIG_HIGH_SCRATCH_MEMORY_SIZE);
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#endif
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#endif
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#if CONFIG_MULTIBOOT
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#if CONFIG_MULTIBOOT
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post_code(0x9d);
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post_code(0x9d);
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