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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1354 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Greg Watson 2004-01-22 01:06:19 +00:00
parent 909472367f
commit 5a8d4ae27c
2 changed files with 10 additions and 8 deletions
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14
src/mainboard/totalimpact/briq/Config.lb
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@ -4,20 +4,26 @@
uses PCIC0_CFGADDR
uses PCIC0_CFGDATA
uses UART0_IO_BASE
uses TTYS0_BASE
uses CONFIG_BRIQ_750FX
uses CONFIG_BRIQ_7400
##
## Set PCI registers
##
default PCIC0_CFGADDR=0xeec00000
default PCIC0_CFGDATA=0xeec00004
default PCIC0_CFGADDR=0xff508000
default PCIC0_CFGDATA=0xff508010
##
## Set IDE control registers
##
default PNP_CFGADDR=0x1f0
default PNP_CFGDATA=0x1f1
##
## Set UART base address
##
default UART0_IO_BASE=0xef600300
default TTYS0_BASE=0x3f8
##
## Early board initialization, called from ppc_main()

4
targets/totalimpact/briq/Config.lb
View File

@ -12,8 +12,6 @@ uses DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_USE_INIT
uses NO_POST
uses CONFIG_CONSOLE_SERIAL8250
uses TTYS0_BASE
uses UART0_IO_BASE
uses CONFIG_IDE_STREAM
uses IDE_BOOT_DRIVE
uses IDE_SWAB IDE_OFFSET
@ -45,8 +43,6 @@ option NO_POST=1
## Enable serial console
option DEFAULT_CONSOLE_LOGLEVEL=8
option CONFIG_CONSOLE_SERIAL8250=1
option UART0_IO_BASE=0x3f0
option TTYS0_BASE=0xfe000000+UART0_IO_BASE
## Boot linux from IDE
option CONFIG_IDE_STREAM=1