diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c
index aaec03cbea..170276ac69 100644
--- a/src/southbridge/amd/cimx/sb800/bootblock.c
+++ b/src/southbridge/amd/cimx/sb800/bootblock.c
@@ -49,10 +49,9 @@ static void enable_rom(void)
 	dword |= (1 << 0) | (1 << 1) | (1 << 4) | (1 << 6) | (1 << 21);
 	pci_io_write_config32(dev, 0x48, dword);
 
-	/* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */
-	/* Set the 4MB enable bits */
+	/* Enable rom access */
 	word = pci_io_read_config16(dev, 0x6c);
-	word = 0xFFC0;
+	word = 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6);
 	pci_io_write_config16(dev, 0x6c, word);
 }
 
diff --git a/src/southbridge/amd/sb800/bootblock.c b/src/southbridge/amd/sb800/bootblock.c
index 82d80f08a8..18eae24312 100644
--- a/src/southbridge/amd/sb800/bootblock.c
+++ b/src/southbridge/amd/sb800/bootblock.c
@@ -57,7 +57,7 @@ static void sb800_enable_rom(void)
 	 * 0xffe0(0000): 2MB
 	 * 0xffc0(0000): 4MB
 	 */
-	pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */
+	pci_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
 	/* Enable LPC ROM range end at 0xffff(ffff). */
 	pci_write_config16(dev, 0x6e, 0xffff);
 }