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soc/amd/genoa/chipset.cb: disable IOMMU devices by default

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Disable the IOMMU PCI devices in the chipset devicetree. In order for
the IOMMU devices on the Onyx mainboard still be enabled, enable them in
the mainboard devicetree.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8c1bbbf370a3b5566a8484bcfa88dc4efa31222b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79409
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2023-12-07 23:19:35 +01:00
parent 2f58bbd686
commit 5aaaee3486
2 changed files with 8 additions and 4 deletions
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4
src/mainboard/amd/onyx/devicetree.cb
View file

@ -53,6 +53,7 @@ chip soc/amd/genoa
}"
device domain 0 on
device ref iommu_0 on end
device ref gpp_bridge_0_0_a on
chip vendorcode/amd/opensil/genoa_poc/mpio # P2
register "start_lane" = "48"
@ -84,6 +85,7 @@ chip soc/amd/genoa
end
device domain 1 on
device ref iommu_1 on end
device ref gpp_bridge_1_0_a on
chip vendorcode/amd/opensil/genoa_poc/mpio # P3
register "start_lane" = "16"
@ -105,6 +107,7 @@ chip soc/amd/genoa
end
device domain 2 on
device ref iommu_2 on end
device ref gpp_bridge_2_0_a on
chip vendorcode/amd/opensil/genoa_poc/mpio # P1
register "start_lane" = "32"
@ -128,6 +131,7 @@ chip soc/amd/genoa
end
device domain 3 on
device ref iommu_3 on end
device ref gpp_bridge_3_0_a on
chip vendorcode/amd/opensil/genoa_poc/mpio # P0
register "start_lane" = "0"

8
src/soc/amd/genoa/chipset.cb
View file

@ -12,7 +12,7 @@ chip soc/amd/genoa
device domain 0 on
ops genoa_pci_domain_ops
device pci 00.0 alias gnb_0 on end
device pci 00.2 alias iommu_0 on ops amd_iommu_ops end
device pci 00.2 alias iommu_0 off ops amd_iommu_ops end
device pci 00.3 alias rcec_0 off end
device pci 01.0 on end # Dummy device function, do not disable
@ -80,7 +80,7 @@ chip soc/amd/genoa
device domain 1 on
ops genoa_pci_domain_ops
device pci 00.0 alias gnb_1 on end
device pci 00.2 alias iommu_1 on ops amd_iommu_ops end
device pci 00.2 alias iommu_1 off ops amd_iommu_ops end
device pci 00.3 alias rcec_1 off end
device pci 01.0 on end # Dummy device function, do not disable
@ -121,7 +121,7 @@ chip soc/amd/genoa
device domain 2 on
ops genoa_pci_domain_ops
device pci 00.0 alias gnb_2 on end
device pci 00.2 alias iommu_2 on ops amd_iommu_ops end
device pci 00.2 alias iommu_2 off ops amd_iommu_ops end
device pci 00.3 alias rcec_2 off end
device pci 01.0 on end # Dummy device function, do not disable
@ -162,7 +162,7 @@ chip soc/amd/genoa
device domain 3 on
ops genoa_pci_domain_ops
device pci 00.0 alias gnb_3 on end
device pci 00.2 alias iommu_3 on ops amd_iommu_ops end
device pci 00.2 alias iommu_3 off ops amd_iommu_ops end
device pci 00.3 alias rcec_3 off end
device pci 01.0 on end # Dummy device function, do not disable