am335x: Add pinmux support based on the functions in U-Boot
I was unable to find documentation that said what mode numbers correspond to what functionality, so I translated over what U-Boot does. Change-Id: I34fab0f024fa2322d6bb66106aed75224e67354d Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3489 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
parent
56892fc475
commit
5acc76cd3e
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@ -1,5 +1,6 @@
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bootblock-y += dmtimer.c
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bootblock-y += nand.c
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bootblock-y += pinmux.c
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bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c
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romstage-y += nand.c
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@ -0,0 +1,190 @@
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/*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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* Copyright (C) 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include "pinmux.h"
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#include <arch/io.h>
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#include <config.h>
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static struct am335x_pinmux_regs *regs =
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(struct am335x_pinmux_regs *)(uintptr_t)AM335X_PINMUX_REG_ADDR;
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void am335x_pinmux_uart0(void)
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{
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writel(MODE(0) | PULLUP_EN | RXACTIVE, ®s->uart0_rxd);
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writel(MODE(0) | PULLUDEN, ®s->uart0_txd);
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}
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void am335x_pinmux_uart1(void)
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{
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writel(MODE(0) | PULLUP_EN | RXACTIVE, ®s->uart1_rxd);
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writel(MODE(0) | PULLUDEN, ®s->uart1_txd);
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}
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void am335x_pinmux_uart2(void)
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{
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// UART2_RXD
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writel(MODE(1) | PULLUP_EN | RXACTIVE, ®s->spi0_sclk);
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// UART2_TXD
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writel(MODE(1) | PULLUDEN, ®s->spi0_d0);
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}
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void am335x_pinmux_uart3(void)
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{
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// UART3_RXD
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writel(MODE(1) | PULLUP_EN | RXACTIVE, ®s->spi0_cs1);
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// UART3_TXD
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writel(MODE(1) | PULLUDEN, ®s->ecap0_in_pwm0_out);
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}
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void am335x_pinmux_uart4(void)
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{
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// UART4_RXD
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writel(MODE(6) | PULLUP_EN | RXACTIVE, ®s->gpmc_wait0);
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// UART4_TXD
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writel(MODE(6) | PULLUDEN, ®s->gpmc_wpn);
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}
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void am335x_pinmux_uart5(void)
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{
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// UART5_RXD
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writel(MODE(4) | PULLUP_EN | RXACTIVE, ®s->lcd_data9);
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// UART5_TXD
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writel(MODE(4) | PULLUDEN, ®s->lcd_data8);
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}
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void am335x_pinmux_mmc0(int cd, int sk_evm)
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{
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writel(MODE(0) | RXACTIVE | PULLUP_EN, ®s->mmc0_dat0);
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writel(MODE(0) | RXACTIVE | PULLUP_EN, ®s->mmc0_dat1);
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writel(MODE(0) | RXACTIVE | PULLUP_EN, ®s->mmc0_dat2);
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writel(MODE(0) | RXACTIVE | PULLUP_EN, ®s->mmc0_dat3);
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writel(MODE(0) | RXACTIVE | PULLUP_EN, ®s->mmc0_clk);
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writel(MODE(0) | RXACTIVE | PULLUP_EN, ®s->mmc0_cmd);
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if (!sk_evm) {
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// MMC0_WP
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writel(MODE(4) | RXACTIVE, ®s->mcasp0_aclkr);
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}
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if (cd) {
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// MMC0_CD
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writel(MODE(5) | RXACTIVE | PULLUP_EN, ®s->spi0_cs1);
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}
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}
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void am335x_pinmux_mmc1(void)
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{
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// MMC1_DAT0
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writel(MODE(1) | RXACTIVE | PULLUP_EN, ®s->gpmc_ad0);
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// MMC1_DAT1
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writel(MODE(1) | RXACTIVE | PULLUP_EN, ®s->gpmc_ad1);
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// MMC1_DAT2
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writel(MODE(1) | RXACTIVE | PULLUP_EN, ®s->gpmc_ad2);
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// MMC1_DAT3
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writel(MODE(1) | RXACTIVE | PULLUP_EN, ®s->gpmc_ad3);
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// MMC1_CLK
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writel(MODE(2) | RXACTIVE | PULLUP_EN, ®s->gpmc_csn1);
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// MMC1_CMD
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writel(MODE(2) | RXACTIVE | PULLUP_EN, ®s->gpmc_csn2);
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// MMC1_WP
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writel(MODE(7) | RXACTIVE | PULLUP_EN, ®s->gpmc_csn0);
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// MMC1_CD
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writel(MODE(7) | RXACTIVE | PULLUP_EN, ®s->gpmc_advn_ale);
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}
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void am335x_pinmux_i2c0(void)
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{
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writel(MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL, ®s->i2c0_sda);
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writel(MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL, ®s->i2c0_scl);
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}
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void am335x_pinmux_i2c1(void)
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{
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// I2C_DATA
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writel(MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL, ®s->spi0_d1);
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// I2C_SCLK
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writel(MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL, ®s->spi0_cs0);
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}
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void am335x_pinmux_spi0(void)
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{
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writel(MODE(0) | RXACTIVE | PULLUDEN, ®s->spi0_sclk);
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writel(MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN, ®s->spi0_d0);
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writel(MODE(0) | RXACTIVE | PULLUDEN, ®s->spi0_d1);
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writel(MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN, ®s->spi0_cs0);
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}
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void am335x_pinmux_gpio0_7(void)
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{
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writel(MODE(7) | PULLUDEN, ®s->ecap0_in_pwm0_out);
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}
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void am335x_pinmux_rgmii1(void)
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{
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writel(MODE(2), ®s->mii1_txen);
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writel(MODE(2) | RXACTIVE, ®s->mii1_rxdv);
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writel(MODE(2), ®s->mii1_txd0);
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writel(MODE(2), ®s->mii1_txd1);
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writel(MODE(2), ®s->mii1_txd2);
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writel(MODE(2), ®s->mii1_txd3);
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writel(MODE(2), ®s->mii1_txclk);
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writel(MODE(2) | RXACTIVE, ®s->mii1_rxclk);
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writel(MODE(2) | RXACTIVE, ®s->mii1_rxd0);
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writel(MODE(2) | RXACTIVE, ®s->mii1_rxd1);
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writel(MODE(2) | RXACTIVE, ®s->mii1_rxd2);
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writel(MODE(2) | RXACTIVE, ®s->mii1_rxd3);
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}
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void am335x_pinmux_mii1(void)
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{
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writel(MODE(0) | RXACTIVE, ®s->mii1_rxerr);
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writel(MODE(0), ®s->mii1_txen);
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writel(MODE(0) | RXACTIVE, ®s->mii1_rxdv);
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writel(MODE(0), ®s->mii1_txd0);
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writel(MODE(0), ®s->mii1_txd1);
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writel(MODE(0), ®s->mii1_txd2);
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writel(MODE(0), ®s->mii1_txd3);
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writel(MODE(0) | RXACTIVE, ®s->mii1_txclk);
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writel(MODE(0) | RXACTIVE, ®s->mii1_rxclk);
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writel(MODE(0) | RXACTIVE, ®s->mii1_rxd0);
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writel(MODE(0) | RXACTIVE, ®s->mii1_rxd1);
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writel(MODE(0) | RXACTIVE, ®s->mii1_rxd2);
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writel(MODE(0) | RXACTIVE, ®s->mii1_rxd3);
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writel(MODE(0) | RXACTIVE | PULLUP_EN, ®s->mdio_data);
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writel(MODE(0) | PULLUP_EN, ®s->mdio_clk);
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}
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void am335x_pinmux_nand(void)
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{
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writel(MODE(0) | PULLUP_EN | RXACTIVE, ®s->gpmc_ad0);
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writel(MODE(0) | PULLUP_EN | RXACTIVE, ®s->gpmc_ad1);
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writel(MODE(0) | PULLUP_EN | RXACTIVE, ®s->gpmc_ad2);
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writel(MODE(0) | PULLUP_EN | RXACTIVE, ®s->gpmc_ad3);
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writel(MODE(0) | PULLUP_EN | RXACTIVE, ®s->gpmc_ad4);
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writel(MODE(0) | PULLUP_EN | RXACTIVE, ®s->gpmc_ad5);
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writel(MODE(0) | PULLUP_EN | RXACTIVE, ®s->gpmc_ad6);
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writel(MODE(0) | PULLUP_EN | RXACTIVE, ®s->gpmc_ad7);
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writel(MODE(0) | RXACTIVE | PULLUP_EN, ®s->gpmc_wait0);
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writel(MODE(7) | PULLUP_EN | RXACTIVE, ®s->gpmc_wpn);
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writel(MODE(0) | PULLUDEN, ®s->gpmc_csn0);
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writel(MODE(0) | PULLUDEN, ®s->gpmc_advn_ale);
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writel(MODE(0) | PULLUDEN, ®s->gpmc_oen_ren);
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writel(MODE(0) | PULLUDEN, ®s->gpmc_wen);
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writel(MODE(0) | PULLUDEN, ®s->gpmc_be0n_cle);
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}
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@ -0,0 +1,268 @@
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/*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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* Copyright (C) 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CPU_TI_AM335X_PINMUX_H
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#define __CPU_TI_AM335X_PINMUX_H
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#include <stdint.h>
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// PAD Control Fields
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#define SLEWCTRL (0x1 << 6)
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#define RXACTIVE (0x1 << 5)
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#define PULLDOWN_EN (0x0 << 4) // Pull down
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#define PULLUP_EN (0x1 << 4) // Pull up
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#define PULLUDEN (0x0 << 3) // Pull up enabled
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#define PULLUDDIS (0x1 << 3) // Pull up disabled
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#define MODE(val) val
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void am335x_pinmux_uart0(void);
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void am335x_pinmux_uart1(void);
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void am335x_pinmux_uart2(void);
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void am335x_pinmux_uart3(void);
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void am335x_pinmux_uart4(void);
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void am335x_pinmux_uart5(void);
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void am335x_pinmux_mmc0(int cd, int sk_evm);
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void am335x_pinmux_mmc1(void);
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void am335x_pinmux_i2c0(void);
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void am335x_pinmux_i2c1(void);
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void am335x_pinmux_spi0(void);
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void am335x_pinmux_gpio0_7(void);
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void am335x_pinmux_rgmii1(void);
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void am335x_pinmux_mii1(void);
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void am335x_pinmux_nand(void);
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#define AM335X_PINMUX_REG_ADDR 0x44e10000
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struct am335x_pinmux_regs {
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uint32_t gpmc_ad0;
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uint32_t gpmc_ad1;
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uint32_t gpmc_ad2;
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uint32_t gpmc_ad3;
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uint32_t gpmc_ad4;
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uint32_t gpmc_ad5;
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uint32_t gpmc_ad6;
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uint32_t gpmc_ad7;
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uint32_t gpmc_ad8;
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uint32_t gpmc_ad9;
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uint32_t gpmc_ad10;
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uint32_t gpmc_ad11;
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uint32_t gpmc_ad12;
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uint32_t gpmc_ad13;
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uint32_t gpmc_ad14;
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uint32_t gpmc_ad15;
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uint32_t gpmc_a0;
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uint32_t gpmc_a1;
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uint32_t gpmc_a2;
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uint32_t gpmc_a3;
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uint32_t gpmc_a4;
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uint32_t gpmc_a5;
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uint32_t gpmc_a6;
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uint32_t gpmc_a7;
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uint32_t gpmc_a8;
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uint32_t gpmc_a9;
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uint32_t gpmc_a10;
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uint32_t gpmc_a11;
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uint32_t gpmc_wait0;
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uint32_t gpmc_wpn;
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uint32_t gpmc_be1n;
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uint32_t gpmc_csn0;
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uint32_t gpmc_csn1;
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uint32_t gpmc_csn2;
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uint32_t gpmc_csn3;
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uint32_t gpmc_clk;
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uint32_t gpmc_advn_ale;
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uint32_t gpmc_oen_ren;
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uint32_t gpmc_wen;
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uint32_t gpmc_be0n_cle;
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uint32_t lcd_data0;
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uint32_t lcd_data1;
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uint32_t lcd_data2;
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uint32_t lcd_data3;
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uint32_t lcd_data4;
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uint32_t lcd_data5;
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uint32_t lcd_data6;
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uint32_t lcd_data7;
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uint32_t lcd_data8;
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uint32_t lcd_data9;
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uint32_t lcd_data10;
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uint32_t lcd_data11;
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uint32_t lcd_data12;
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uint32_t lcd_data13;
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uint32_t lcd_data14;
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uint32_t lcd_data15;
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uint32_t lcd_vsync;
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uint32_t lcd_hsync;
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uint32_t lcd_pclk;
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uint32_t lcd_ac_bias_en;
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uint32_t mmc0_dat3;
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uint32_t mmc0_dat2;
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uint32_t mmc0_dat1;
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uint32_t mmc0_dat0;
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uint32_t mmc0_clk;
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uint32_t mmc0_cmd;
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uint32_t mii1_col;
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uint32_t mii1_crs;
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uint32_t mii1_rxerr;
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uint32_t mii1_txen;
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uint32_t mii1_rxdv;
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uint32_t mii1_txd3;
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uint32_t mii1_txd2;
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uint32_t mii1_txd1;
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uint32_t mii1_txd0;
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uint32_t mii1_txclk;
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uint32_t mii1_rxclk;
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uint32_t mii1_rxd3;
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uint32_t mii1_rxd2;
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uint32_t mii1_rxd1;
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uint32_t mii1_rxd0;
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uint32_t rmii1_refclk;
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uint32_t mdio_data;
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uint32_t mdio_clk;
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uint32_t spi0_sclk;
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uint32_t spi0_d0;
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uint32_t spi0_d1;
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uint32_t spi0_cs0;
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uint32_t spi0_cs1;
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uint32_t ecap0_in_pwm0_out;
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uint32_t uart0_ctsn;
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uint32_t uart0_rtsn;
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uint32_t uart0_rxd;
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uint32_t uart0_txd;
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uint32_t uart1_ctsn;
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uint32_t uart1_rtsn;
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uint32_t uart1_rxd;
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uint32_t uart1_txd;
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uint32_t i2c0_sda;
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uint32_t i2c0_scl;
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uint32_t mcasp0_aclkx;
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uint32_t mcasp0_fsx;
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uint32_t mcasp0_axr0;
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uint32_t mcasp0_ahclkr;
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uint32_t mcasp0_aclkr;
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uint32_t mcasp0_fsr;
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uint32_t mcasp0_axr1;
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uint32_t mcasp0_ahclkx;
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uint32_t xdma_event_intr0;
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uint32_t xdma_event_intr1;
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uint32_t nresetin_out;
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uint32_t porz;
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uint32_t nnmi;
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uint32_t osc0_in;
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uint32_t osc0_out;
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uint32_t rsvd1;
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uint32_t tms;
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uint32_t tdi;
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uint32_t tdo;
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uint32_t tck;
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uint32_t ntrst;
|
||||
uint32_t emu0;
|
||||
uint32_t emu1;
|
||||
uint32_t osc1_in;
|
||||
uint32_t osc1_out;
|
||||
uint32_t pmic_power_en;
|
||||
uint32_t rtc_porz;
|
||||
uint32_t rsvd2;
|
||||
uint32_t ext_wakeup;
|
||||
uint32_t enz_kaldo_1p8v;
|
||||
uint32_t usb0_dm;
|
||||
uint32_t usb0_dp;
|
||||
uint32_t usb0_ce;
|
||||
uint32_t usb0_id;
|
||||
uint32_t usb0_vbus;
|
||||
uint32_t usb0_drvvbus;
|
||||
uint32_t usb1_dm;
|
||||
uint32_t usb1_dp;
|
||||
uint32_t usb1_ce;
|
||||
uint32_t usb1_id;
|
||||
uint32_t usb1_vbus;
|
||||
uint32_t usb1_drvvbus;
|
||||
uint32_t ddr_resetn;
|
||||
uint32_t ddr_csn0;
|
||||
uint32_t ddr_cke;
|
||||
uint32_t ddr_ck;
|
||||
uint32_t ddr_nck;
|
||||
uint32_t ddr_casn;
|
||||
uint32_t ddr_rasn;
|
||||
uint32_t ddr_wen;
|
||||
uint32_t ddr_ba0;
|
||||
uint32_t ddr_ba1;
|
||||
uint32_t ddr_ba2;
|
||||
uint32_t ddr_a0;
|
||||
uint32_t ddr_a1;
|
||||
uint32_t ddr_a2;
|
||||
uint32_t ddr_a3;
|
||||
uint32_t ddr_a4;
|
||||
uint32_t ddr_a5;
|
||||
uint32_t ddr_a6;
|
||||
uint32_t ddr_a7;
|
||||
uint32_t ddr_a8;
|
||||
uint32_t ddr_a9;
|
||||
uint32_t ddr_a10;
|
||||
uint32_t ddr_a11;
|
||||
uint32_t ddr_a12;
|
||||
uint32_t ddr_a13;
|
||||
uint32_t ddr_a14;
|
||||
uint32_t ddr_a15;
|
||||
uint32_t ddr_odt;
|
||||
uint32_t ddr_d0;
|
||||
uint32_t ddr_d1;
|
||||
uint32_t ddr_d2;
|
||||
uint32_t ddr_d3;
|
||||
uint32_t ddr_d4;
|
||||
uint32_t ddr_d5;
|
||||
uint32_t ddr_d6;
|
||||
uint32_t ddr_d7;
|
||||
uint32_t ddr_d8;
|
||||
uint32_t ddr_d9;
|
||||
uint32_t ddr_d10;
|
||||
uint32_t ddr_d11;
|
||||
uint32_t ddr_d12;
|
||||
uint32_t ddr_d13;
|
||||
uint32_t ddr_d14;
|
||||
uint32_t ddr_d15;
|
||||
uint32_t ddr_dqm0;
|
||||
uint32_t ddr_dqm1;
|
||||
uint32_t ddr_dqs0;
|
||||
uint32_t ddr_dqsn0;
|
||||
uint32_t ddr_dqs1;
|
||||
uint32_t ddr_dqsn1;
|
||||
uint32_t ddr_vref;
|
||||
uint32_t ddr_vtp;
|
||||
uint32_t ddr_strben0;
|
||||
uint32_t ddr_strben1;
|
||||
uint32_t ain7;
|
||||
uint32_t ain6;
|
||||
uint32_t ain5;
|
||||
uint32_t ain4;
|
||||
uint32_t ain3;
|
||||
uint32_t ain2;
|
||||
uint32_t ain1;
|
||||
uint32_t ain0;
|
||||
uint32_t vrefp;
|
||||
uint32_t vrefn;
|
||||
};
|
||||
|
||||
#endif
|
Loading…
Reference in New Issue