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am335x: Add pinmux support based on the functions in U-Boot 

I was unable to find documentation that said what mode numbers correspond
to what functionality, so I translated over what U-Boot does.

Change-Id: I34fab0f024fa2322d6bb66106aed75224e67354d
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3489
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Gabe Black 2013-06-17 01:17:55 -07:00 committed by Stefan Reinauer
parent 56892fc475
commit 5acc76cd3e
3 changed files with 459 additions and 0 deletions
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1
src/cpu/ti/am335x/Makefile.inc
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@ -1,5 +1,6 @@
bootblock-y += dmtimer.c bootblock-y += dmtimer.c
bootblock-y += nand.c bootblock-y += nand.c
bootblock-y += pinmux.c
bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c
romstage-y += nand.c romstage-y += nand.c

190
src/cpu/ti/am335x/pinmux.c Normal file
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@ -0,0 +1,190 @@
/*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include "pinmux.h"
#include <arch/io.h>
#include <config.h>
static struct am335x_pinmux_regs *regs =
(struct am335x_pinmux_regs *)(uintptr_t)AM335X_PINMUX_REG_ADDR;
void am335x_pinmux_uart0(void)
{
writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->uart0_rxd);
writel(MODE(0) | PULLUDEN, &regs->uart0_txd);
}
void am335x_pinmux_uart1(void)
{
writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->uart1_rxd);
writel(MODE(0) | PULLUDEN, &regs->uart1_txd);
}
void am335x_pinmux_uart2(void)
{
// UART2_RXD
writel(MODE(1) | PULLUP_EN | RXACTIVE, &regs->spi0_sclk);
// UART2_TXD
writel(MODE(1) | PULLUDEN, &regs->spi0_d0);
}
void am335x_pinmux_uart3(void)
{
// UART3_RXD
writel(MODE(1) | PULLUP_EN | RXACTIVE, &regs->spi0_cs1);
// UART3_TXD
writel(MODE(1) | PULLUDEN, &regs->ecap0_in_pwm0_out);
}
void am335x_pinmux_uart4(void)
{
// UART4_RXD
writel(MODE(6) | PULLUP_EN | RXACTIVE, &regs->gpmc_wait0);
// UART4_TXD
writel(MODE(6) | PULLUDEN, &regs->gpmc_wpn);
}
void am335x_pinmux_uart5(void)
{
// UART5_RXD
writel(MODE(4) | PULLUP_EN | RXACTIVE, &regs->lcd_data9);
// UART5_TXD
writel(MODE(4) | PULLUDEN, &regs->lcd_data8);
}
void am335x_pinmux_mmc0(int cd, int sk_evm)
{
writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_dat0);
writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_dat1);
writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_dat2);
writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_dat3);
writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_clk);
writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_cmd);
if (!sk_evm) {
// MMC0_WP
writel(MODE(4) | RXACTIVE, &regs->mcasp0_aclkr);
}
if (cd) {
// MMC0_CD
writel(MODE(5) | RXACTIVE | PULLUP_EN, &regs->spi0_cs1);
}
}
void am335x_pinmux_mmc1(void)
{
// MMC1_DAT0
writel(MODE(1) | RXACTIVE | PULLUP_EN, &regs->gpmc_ad0);
// MMC1_DAT1
writel(MODE(1) | RXACTIVE | PULLUP_EN, &regs->gpmc_ad1);
// MMC1_DAT2
writel(MODE(1) | RXACTIVE | PULLUP_EN, &regs->gpmc_ad2);
// MMC1_DAT3
writel(MODE(1) | RXACTIVE | PULLUP_EN, &regs->gpmc_ad3);
// MMC1_CLK
writel(MODE(2) | RXACTIVE | PULLUP_EN, &regs->gpmc_csn1);
// MMC1_CMD
writel(MODE(2) | RXACTIVE | PULLUP_EN, &regs->gpmc_csn2);
// MMC1_WP
writel(MODE(7) | RXACTIVE | PULLUP_EN, &regs->gpmc_csn0);
// MMC1_CD
writel(MODE(7) | RXACTIVE | PULLUP_EN, &regs->gpmc_advn_ale);
}
void am335x_pinmux_i2c0(void)
{
writel(MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL, &regs->i2c0_sda);
writel(MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL, &regs->i2c0_scl);
}
void am335x_pinmux_i2c1(void)
{
// I2C_DATA
writel(MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL, &regs->spi0_d1);
// I2C_SCLK
writel(MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL, &regs->spi0_cs0);
}
void am335x_pinmux_spi0(void)
{
writel(MODE(0) | RXACTIVE | PULLUDEN, &regs->spi0_sclk);
writel(MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN, &regs->spi0_d0);
writel(MODE(0) | RXACTIVE | PULLUDEN, &regs->spi0_d1);
writel(MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN, &regs->spi0_cs0);
}
void am335x_pinmux_gpio0_7(void)
{
writel(MODE(7) | PULLUDEN, &regs->ecap0_in_pwm0_out);
}
void am335x_pinmux_rgmii1(void)
{
writel(MODE(2), &regs->mii1_txen);
writel(MODE(2) | RXACTIVE, &regs->mii1_rxdv);
writel(MODE(2), &regs->mii1_txd0);
writel(MODE(2), &regs->mii1_txd1);
writel(MODE(2), &regs->mii1_txd2);
writel(MODE(2), &regs->mii1_txd3);
writel(MODE(2), &regs->mii1_txclk);
writel(MODE(2) | RXACTIVE, &regs->mii1_rxclk);
writel(MODE(2) | RXACTIVE, &regs->mii1_rxd0);
writel(MODE(2) | RXACTIVE, &regs->mii1_rxd1);
writel(MODE(2) | RXACTIVE, &regs->mii1_rxd2);
writel(MODE(2) | RXACTIVE, &regs->mii1_rxd3);
}
void am335x_pinmux_mii1(void)
{
writel(MODE(0) | RXACTIVE, &regs->mii1_rxerr);
writel(MODE(0), &regs->mii1_txen);
writel(MODE(0) | RXACTIVE, &regs->mii1_rxdv);
writel(MODE(0), &regs->mii1_txd0);
writel(MODE(0), &regs->mii1_txd1);
writel(MODE(0), &regs->mii1_txd2);
writel(MODE(0), &regs->mii1_txd3);
writel(MODE(0) | RXACTIVE, &regs->mii1_txclk);
writel(MODE(0) | RXACTIVE, &regs->mii1_rxclk);
writel(MODE(0) | RXACTIVE, &regs->mii1_rxd0);
writel(MODE(0) | RXACTIVE, &regs->mii1_rxd1);
writel(MODE(0) | RXACTIVE, &regs->mii1_rxd2);
writel(MODE(0) | RXACTIVE, &regs->mii1_rxd3);
writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mdio_data);
writel(MODE(0) | PULLUP_EN, &regs->mdio_clk);
}
void am335x_pinmux_nand(void)
{
writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad0);
writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad1);
writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad2);
writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad3);
writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad4);
writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad5);
writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad6);
writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad7);
writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->gpmc_wait0);
writel(MODE(7) | PULLUP_EN | RXACTIVE, &regs->gpmc_wpn);
writel(MODE(0) | PULLUDEN, &regs->gpmc_csn0);
writel(MODE(0) | PULLUDEN, &regs->gpmc_advn_ale);
writel(MODE(0) | PULLUDEN, &regs->gpmc_oen_ren);
writel(MODE(0) | PULLUDEN, &regs->gpmc_wen);
writel(MODE(0) | PULLUDEN, &regs->gpmc_be0n_cle);
}

268
src/cpu/ti/am335x/pinmux.h Normal file
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@ -0,0 +1,268 @@
/*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CPU_TI_AM335X_PINMUX_H
#define __CPU_TI_AM335X_PINMUX_H
#include <stdint.h>
// PAD Control Fields
#define SLEWCTRL (0x1 << 6)
#define RXACTIVE (0x1 << 5)
#define PULLDOWN_EN (0x0 << 4) // Pull down
#define PULLUP_EN (0x1 << 4) // Pull up
#define PULLUDEN (0x0 << 3) // Pull up enabled
#define PULLUDDIS (0x1 << 3) // Pull up disabled
#define MODE(val) val
void am335x_pinmux_uart0(void);
void am335x_pinmux_uart1(void);
void am335x_pinmux_uart2(void);
void am335x_pinmux_uart3(void);
void am335x_pinmux_uart4(void);
void am335x_pinmux_uart5(void);
void am335x_pinmux_mmc0(int cd, int sk_evm);
void am335x_pinmux_mmc1(void);
void am335x_pinmux_i2c0(void);
void am335x_pinmux_i2c1(void);
void am335x_pinmux_spi0(void);
void am335x_pinmux_gpio0_7(void);
void am335x_pinmux_rgmii1(void);
void am335x_pinmux_mii1(void);
void am335x_pinmux_nand(void);
#define AM335X_PINMUX_REG_ADDR 0x44e10000
struct am335x_pinmux_regs {
uint32_t gpmc_ad0;
uint32_t gpmc_ad1;
uint32_t gpmc_ad2;
uint32_t gpmc_ad3;
uint32_t gpmc_ad4;
uint32_t gpmc_ad5;
uint32_t gpmc_ad6;
uint32_t gpmc_ad7;
uint32_t gpmc_ad8;
uint32_t gpmc_ad9;
uint32_t gpmc_ad10;
uint32_t gpmc_ad11;
uint32_t gpmc_ad12;
uint32_t gpmc_ad13;
uint32_t gpmc_ad14;
uint32_t gpmc_ad15;
uint32_t gpmc_a0;
uint32_t gpmc_a1;
uint32_t gpmc_a2;
uint32_t gpmc_a3;
uint32_t gpmc_a4;
uint32_t gpmc_a5;
uint32_t gpmc_a6;
uint32_t gpmc_a7;
uint32_t gpmc_a8;
uint32_t gpmc_a9;
uint32_t gpmc_a10;
uint32_t gpmc_a11;
uint32_t gpmc_wait0;
uint32_t gpmc_wpn;
uint32_t gpmc_be1n;
uint32_t gpmc_csn0;
uint32_t gpmc_csn1;
uint32_t gpmc_csn2;
uint32_t gpmc_csn3;
uint32_t gpmc_clk;
uint32_t gpmc_advn_ale;
uint32_t gpmc_oen_ren;
uint32_t gpmc_wen;
uint32_t gpmc_be0n_cle;
uint32_t lcd_data0;
uint32_t lcd_data1;
uint32_t lcd_data2;
uint32_t lcd_data3;
uint32_t lcd_data4;
uint32_t lcd_data5;
uint32_t lcd_data6;
uint32_t lcd_data7;
uint32_t lcd_data8;
uint32_t lcd_data9;
uint32_t lcd_data10;
uint32_t lcd_data11;
uint32_t lcd_data12;
uint32_t lcd_data13;
uint32_t lcd_data14;
uint32_t lcd_data15;
uint32_t lcd_vsync;
uint32_t lcd_hsync;
uint32_t lcd_pclk;
uint32_t lcd_ac_bias_en;
uint32_t mmc0_dat3;
uint32_t mmc0_dat2;
uint32_t mmc0_dat1;
uint32_t mmc0_dat0;
uint32_t mmc0_clk;
uint32_t mmc0_cmd;
uint32_t mii1_col;
uint32_t mii1_crs;
uint32_t mii1_rxerr;
uint32_t mii1_txen;
uint32_t mii1_rxdv;
uint32_t mii1_txd3;
uint32_t mii1_txd2;
uint32_t mii1_txd1;
uint32_t mii1_txd0;
uint32_t mii1_txclk;
uint32_t mii1_rxclk;
uint32_t mii1_rxd3;
uint32_t mii1_rxd2;
uint32_t mii1_rxd1;
uint32_t mii1_rxd0;
uint32_t rmii1_refclk;
uint32_t mdio_data;
uint32_t mdio_clk;
uint32_t spi0_sclk;
uint32_t spi0_d0;
uint32_t spi0_d1;
uint32_t spi0_cs0;
uint32_t spi0_cs1;
uint32_t ecap0_in_pwm0_out;
uint32_t uart0_ctsn;
uint32_t uart0_rtsn;
uint32_t uart0_rxd;
uint32_t uart0_txd;
uint32_t uart1_ctsn;
uint32_t uart1_rtsn;
uint32_t uart1_rxd;
uint32_t uart1_txd;
uint32_t i2c0_sda;
uint32_t i2c0_scl;
uint32_t mcasp0_aclkx;
uint32_t mcasp0_fsx;
uint32_t mcasp0_axr0;
uint32_t mcasp0_ahclkr;
uint32_t mcasp0_aclkr;
uint32_t mcasp0_fsr;
uint32_t mcasp0_axr1;
uint32_t mcasp0_ahclkx;
uint32_t xdma_event_intr0;
uint32_t xdma_event_intr1;
uint32_t nresetin_out;
uint32_t porz;
uint32_t nnmi;
uint32_t osc0_in;
uint32_t osc0_out;
uint32_t rsvd1;
uint32_t tms;
uint32_t tdi;
uint32_t tdo;
uint32_t tck;
uint32_t ntrst;
uint32_t emu0;
uint32_t emu1;
uint32_t osc1_in;
uint32_t osc1_out;
uint32_t pmic_power_en;
uint32_t rtc_porz;
uint32_t rsvd2;
uint32_t ext_wakeup;
uint32_t enz_kaldo_1p8v;
uint32_t usb0_dm;
uint32_t usb0_dp;
uint32_t usb0_ce;
uint32_t usb0_id;
uint32_t usb0_vbus;
uint32_t usb0_drvvbus;
uint32_t usb1_dm;
uint32_t usb1_dp;
uint32_t usb1_ce;
uint32_t usb1_id;
uint32_t usb1_vbus;
uint32_t usb1_drvvbus;
uint32_t ddr_resetn;
uint32_t ddr_csn0;
uint32_t ddr_cke;
uint32_t ddr_ck;
uint32_t ddr_nck;
uint32_t ddr_casn;
uint32_t ddr_rasn;
uint32_t ddr_wen;
uint32_t ddr_ba0;
uint32_t ddr_ba1;
uint32_t ddr_ba2;
uint32_t ddr_a0;
uint32_t ddr_a1;
uint32_t ddr_a2;
uint32_t ddr_a3;
uint32_t ddr_a4;
uint32_t ddr_a5;
uint32_t ddr_a6;
uint32_t ddr_a7;
uint32_t ddr_a8;
uint32_t ddr_a9;
uint32_t ddr_a10;
uint32_t ddr_a11;
uint32_t ddr_a12;
uint32_t ddr_a13;
uint32_t ddr_a14;
uint32_t ddr_a15;
uint32_t ddr_odt;
uint32_t ddr_d0;
uint32_t ddr_d1;
uint32_t ddr_d2;
uint32_t ddr_d3;
uint32_t ddr_d4;
uint32_t ddr_d5;
uint32_t ddr_d6;
uint32_t ddr_d7;
uint32_t ddr_d8;
uint32_t ddr_d9;
uint32_t ddr_d10;
uint32_t ddr_d11;
uint32_t ddr_d12;
uint32_t ddr_d13;
uint32_t ddr_d14;
uint32_t ddr_d15;
uint32_t ddr_dqm0;
uint32_t ddr_dqm1;
uint32_t ddr_dqs0;
uint32_t ddr_dqsn0;
uint32_t ddr_dqs1;
uint32_t ddr_dqsn1;
uint32_t ddr_vref;
uint32_t ddr_vtp;
uint32_t ddr_strben0;
uint32_t ddr_strben1;
uint32_t ain7;
uint32_t ain6;
uint32_t ain5;
uint32_t ain4;
uint32_t ain3;
uint32_t ain2;
uint32_t ain1;
uint32_t ain0;
uint32_t vrefp;
uint32_t vrefn;
};
#endif