From 5ad85d95cd656996acbfef5c8bea791662b551cd Mon Sep 17 00:00:00 2001
From: Karthikeyan Ramasubramanian <kramasub@google.com>
Date: Thu, 22 Apr 2021 16:59:08 -0600
Subject: [PATCH] soc/amd/cezanne/fsp_m_params: Configure the s0i3_enable UPD

Configure the S0i3 enable UPD based on the mainboard configuration.

BUG=b:178728116
TEST=Build and boot to OS in Guybrush. Enter S0i3 after passing the
sleep state configuration from the mainboard.

Change-Id: I18f43e964d1c70317155394257a5e2c1900816bb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
---
 src/soc/amd/cezanne/fsp_m_params.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c
index 9d4159d85b..a83b8b2f57 100644
--- a/src/soc/amd/cezanne/fsp_m_params.c
+++ b/src/soc/amd/cezanne/fsp_m_params.c
@@ -113,5 +113,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	mcfg->cppc_epp_min_range = config->cppc_epp_min_range;
 	mcfg->cppc_preferred_cores = config->cppc_preferred_cores;
 
+	/* S0i3 enable */
+	mcfg->s0i3_enable = config->s0ix_enable;
+
 	fsp_fill_pcie_ddi_descriptors(mcfg);
 }