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amd/inagua: Switch away from AGESA_LEGACY 

Change-Id: Ie76291a8e227e49aae6fc6339cec2009ebd67fff
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Kyösti Mälkki 2017-03-04 07:50:33 +02:00
parent 15a462b662
commit 5aeaeb9560
3 changed files with 11 additions and 70 deletions
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1
src/mainboard/amd/inagua/Kconfig
View File

@ -17,7 +17,6 @@ if BOARD_AMD_INAGUA
config BOARD_SPECIFIC_OPTIONS # dummy config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y def_bool y
select AGESA_LEGACY
select CPU_AMD_AGESA_FAMILY14 select CPU_AMD_AGESA_FAMILY14
select NORTHBRIDGE_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14
select SOUTHBRIDGE_AMD_CIMX_SB800 select SOUTHBRIDGE_AMD_CIMX_SB800

14
src/mainboard/amd/inagua/OemCustomize.c
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@ -16,7 +16,7 @@
#include "PlatformGnbPcieComplex.h" #include "PlatformGnbPcieComplex.h"
#include <string.h> #include <string.h>
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/state_machine.h>
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
@ -38,7 +38,7 @@
**/ **/
/*---------------------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------------------*/
static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
VOID *BrazosPcieComplexListPtr; VOID *BrazosPcieComplexListPtr;
@ -126,7 +126,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
InitEarly->GnbConfig.PsppPolicy = 0; InitEarly->GnbConfig.PsppPolicy = 0;
return AGESA_SUCCESS;
} }
/*---------------------------------------------------------------------------------------- /*----------------------------------------------------------------------------------------
@ -140,12 +139,13 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings. * use its default conservative settings.
*/ */
CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
PSO_END PSO_END
}; };
const struct OEM_HOOK OemCustomize = { void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
.InitEarly = OemInitEarly, {
}; InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
}

66
src/mainboard/amd/inagua/romstage.c
View File

@ -13,72 +13,14 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <lib.h>
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include <arch/stages.h>
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <arch/cpu.h> #include <northbridge/amd/agesa/state_machine.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <cpu/x86/bist.h>
#include <superio/smsc/kbc1100/kbc1100.h> #include <superio/smsc/kbc1100/kbc1100.h>
#include <cpu/x86/lapic.h>
#include <sb_cimx.h>
#include "SBPLATFORM.h"
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void board_BeforeAgesa(struct sysinfo *cb)
{ {
u32 val; kbc1100_early_init(0x2e);
kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
/* Must come first to enable PCI MMCONF. */
amd_initmmio();
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
sb_Poweron_Init();
post_code(0x31);
kbc1100_early_init(0x2e);
kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
}
/* Halt if there was a built in self test failure */
post_code(0x34);
report_bist_failure(bist);
/* Load MPB */
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x37);
agesawrapper_amdinitreset();
post_code(0x39);
agesawrapper_amdinitearly();
post_code(0x40);
agesawrapper_amdinitpost();
post_code(0x41);
agesawrapper_amdinitenv();
amd_initenv();
post_code(0x50);
copy_and_run();
printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
post_code(0x54); /* Should never see this post code. */
} }