mb/hp/8460p: Transform into variant
Tested with BUILD_TIMELESS=1, binary does not change. Change-Id: I17b6ac9ac2433b760e125a1ce708d3b422b632b5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons
Nico Huber
parent
a3580e59be
commit
5aee8262d5
|
|
@ -1,63 +0,0 @@
|
||||||
#
|
|
||||||
# This file is part of the coreboot project.
|
|
||||||
#
|
|
||||||
# Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
|
|
||||||
#
|
|
||||||
# This program is free software; you can redistribute it and/or modify
|
|
||||||
# it under the terms of the GNU General Public License as published by
|
|
||||||
# the Free Software Foundation; version 2 of the License.
|
|
||||||
#
|
|
||||||
# This program is distributed in the hope that it will be useful,
|
|
||||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
# GNU General Public License for more details.
|
|
||||||
#
|
|
||||||
|
|
||||||
if BOARD_HP_8460P
|
|
||||||
|
|
||||||
config BOARD_SPECIFIC_OPTIONS
|
|
||||||
def_bool y
|
|
||||||
select BOARD_ROMSIZE_KB_8192
|
|
||||||
select EC_HP_KBC1126
|
|
||||||
select GFX_GMA_INTERNAL_IS_LVDS
|
|
||||||
select HAVE_ACPI_RESUME
|
|
||||||
select HAVE_ACPI_TABLES
|
|
||||||
select HAVE_CMOS_DEFAULT
|
|
||||||
select HAVE_OPTION_TABLE
|
|
||||||
select INTEL_INT15
|
|
||||||
select MAINBOARD_HAS_LIBGFXINIT
|
|
||||||
select MAINBOARD_HAS_LPC_TPM
|
|
||||||
select MAINBOARD_HAS_TPM1
|
|
||||||
select MAINBOARD_USES_IFD_GBE_REGION
|
|
||||||
select NORTHBRIDGE_INTEL_SANDYBRIDGE
|
|
||||||
select SERIRQ_CONTINUOUS_MODE
|
|
||||||
select SOUTHBRIDGE_INTEL_BD82X6X
|
|
||||||
select SUPERIO_SMSC_LPC47N217
|
|
||||||
select SYSTEM_TYPE_LAPTOP
|
|
||||||
select USE_NATIVE_RAMINIT
|
|
||||||
|
|
||||||
config MAINBOARD_DIR
|
|
||||||
string
|
|
||||||
default "hp/8460p"
|
|
||||||
|
|
||||||
config MAINBOARD_PART_NUMBER
|
|
||||||
string
|
|
||||||
default "EliteBook 8460p"
|
|
||||||
|
|
||||||
config VGA_BIOS_FILE
|
|
||||||
string
|
|
||||||
default "pci8086,0116.rom"
|
|
||||||
|
|
||||||
config VGA_BIOS_ID
|
|
||||||
string
|
|
||||||
default "8086,0116"
|
|
||||||
|
|
||||||
config MAX_CPUS
|
|
||||||
int
|
|
||||||
default 8
|
|
||||||
|
|
||||||
config USBDEBUG_HCD_INDEX
|
|
||||||
int
|
|
||||||
default 1
|
|
||||||
|
|
||||||
endif
|
|
||||||
|
|
@ -1,2 +0,0 @@
|
||||||
config BOARD_HP_8460P
|
|
||||||
bool "EliteBook 8460p"
|
|
||||||
|
|
@ -1,21 +0,0 @@
|
||||||
##
|
|
||||||
## This file is part of the coreboot project.
|
|
||||||
##
|
|
||||||
## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
|
|
||||||
##
|
|
||||||
## This program is free software; you can redistribute it and/or modify
|
|
||||||
## it under the terms of the GNU General Public License as published by
|
|
||||||
## the Free Software Foundation; version 2 of the License.
|
|
||||||
##
|
|
||||||
## This program is distributed in the hope that it will be useful,
|
|
||||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
## GNU General Public License for more details.
|
|
||||||
##
|
|
||||||
|
|
||||||
bootblock-y += gpio.c
|
|
||||||
romstage-y += gpio.c
|
|
||||||
|
|
||||||
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
|
|
||||||
bootblock-y += early_init.c
|
|
||||||
romstage-y += early_init.c
|
|
||||||
|
|
@ -1,16 +0,0 @@
|
||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <ec/hp/kbc1126/acpi/ec.asl>
|
|
||||||
|
|
@ -1,27 +0,0 @@
|
||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
Method(_WAK,1)
|
|
||||||
{
|
|
||||||
\_SB.PCI0.LPCB.EC0.ACPI = 1
|
|
||||||
\_SB.PCI0.LPCB.EC0.SLPT = 0
|
|
||||||
|
|
||||||
Return(Package(){0,0})
|
|
||||||
}
|
|
||||||
|
|
||||||
Method(_PTS,1)
|
|
||||||
{
|
|
||||||
\_SB.PCI0.LPCB.EC0.SLPT = Arg0
|
|
||||||
}
|
|
||||||
|
|
@ -1,16 +0,0 @@
|
||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007-2009 coresystems GmbH
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <drivers/pc80/pc/ps2_controller.asl>
|
|
||||||
|
|
@ -1,27 +0,0 @@
|
||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2008-2009 coresystems GmbH
|
|
||||||
* Copyright (C) 2014 Vladimir Serbinenko
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or
|
|
||||||
* modify it under the terms of the GNU General Public License as
|
|
||||||
* published by the Free Software Foundation; version 2 of
|
|
||||||
* the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <southbridge/intel/bd82x6x/nvs.h>
|
|
||||||
|
|
||||||
void acpi_create_gnvs(global_nvs_t *gnvs)
|
|
||||||
{
|
|
||||||
// the lid is open by default.
|
|
||||||
gnvs->lids = 1;
|
|
||||||
|
|
||||||
gnvs->tcrt = 100;
|
|
||||||
gnvs->tpsv = 90;
|
|
||||||
}
|
|
||||||
|
|
@ -1,6 +0,0 @@
|
||||||
boot_option=Fallback
|
|
||||||
debug_level=Debug
|
|
||||||
power_on_after_fail=Disable
|
|
||||||
nmi=Enable
|
|
||||||
volume=0x3
|
|
||||||
sata_mode=AHCI
|
|
||||||
|
|
@ -1,116 +0,0 @@
|
||||||
##
|
|
||||||
## This file is part of the coreboot project.
|
|
||||||
##
|
|
||||||
## Copyright (C) 2007-2008 coresystems GmbH
|
|
||||||
## Copyright (C) 2014 Vladimir Serbinenko
|
|
||||||
##
|
|
||||||
## This program is free software; you can redistribute it and/or modify
|
|
||||||
## it under the terms of the GNU General Public License as published by
|
|
||||||
## the Free Software Foundation; version 2 of the License.
|
|
||||||
##
|
|
||||||
## This program is distributed in the hope that it will be useful,
|
|
||||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
## GNU General Public License for more details.
|
|
||||||
##
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
entries
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# Status Register A
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# Status Register B
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# Status Register C
|
|
||||||
#96 4 r 0 status_c_rsvd
|
|
||||||
#100 1 r 0 uf_flag
|
|
||||||
#101 1 r 0 af_flag
|
|
||||||
#102 1 r 0 pf_flag
|
|
||||||
#103 1 r 0 irqf_flag
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# Status Register D
|
|
||||||
#104 7 r 0 status_d_rsvd
|
|
||||||
#111 1 r 0 valid_cmos_ram
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# Diagnostic Status Register
|
|
||||||
#112 8 r 0 diag_rsvd1
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
0 120 r 0 reserved_memory
|
|
||||||
#120 264 r 0 unused
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
|
||||||
384 1 e 4 boot_option
|
|
||||||
388 4 h 0 reboot_counter
|
|
||||||
#390 2 r 0 unused?
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
# coreboot config options: console
|
|
||||||
#392 3 r 0 unused
|
|
||||||
395 4 e 6 debug_level
|
|
||||||
#399 1 r 0 unused
|
|
||||||
|
|
||||||
#400 8 r 0 reserved for century byte
|
|
||||||
|
|
||||||
# coreboot config options: southbridge
|
|
||||||
408 1 e 1 nmi
|
|
||||||
409 2 e 7 power_on_after_fail
|
|
||||||
|
|
||||||
421 1 e 9 sata_mode
|
|
||||||
|
|
||||||
# coreboot config options: cpu
|
|
||||||
#424 8 r 0 unused
|
|
||||||
|
|
||||||
# coreboot config options: northbridge
|
|
||||||
432 3 e 11 gfx_uma_size
|
|
||||||
#435 5 r 0 unused
|
|
||||||
|
|
||||||
440 8 h 0 volume
|
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
|
||||||
896 32 r 0 mrc_scrambler_seed
|
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
|
||||||
960 16 r 0 mrc_scrambler_seed_chk
|
|
||||||
|
|
||||||
# coreboot config options: check sums
|
|
||||||
984 16 h 0 check_sum
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
|
|
||||||
enumerations
|
|
||||||
|
|
||||||
#ID value text
|
|
||||||
1 0 Disable
|
|
||||||
1 1 Enable
|
|
||||||
2 0 Enable
|
|
||||||
2 1 Disable
|
|
||||||
4 0 Fallback
|
|
||||||
4 1 Normal
|
|
||||||
6 0 Emergency
|
|
||||||
6 1 Alert
|
|
||||||
6 2 Critical
|
|
||||||
6 3 Error
|
|
||||||
6 4 Warning
|
|
||||||
6 5 Notice
|
|
||||||
6 6 Info
|
|
||||||
6 7 Debug
|
|
||||||
6 8 Spew
|
|
||||||
7 0 Disable
|
|
||||||
7 1 Enable
|
|
||||||
7 2 Keep
|
|
||||||
9 0 AHCI
|
|
||||||
9 1 Compatible
|
|
||||||
11 0 32M
|
|
||||||
11 1 64M
|
|
||||||
11 2 96M
|
|
||||||
11 3 128M
|
|
||||||
11 4 160M
|
|
||||||
11 5 192M
|
|
||||||
11 6 224M
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
checksums
|
|
||||||
|
|
||||||
checksum 392 447 984
|
|
||||||
|
|
@ -1,44 +0,0 @@
|
||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007-2009 coresystems GmbH
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
|
|
||||||
#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
|
|
||||||
#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
|
|
||||||
#include <arch/acpi.h>
|
|
||||||
DefinitionBlock(
|
|
||||||
"dsdt.aml",
|
|
||||||
"DSDT",
|
|
||||||
0x02, // DSDT revision: ACPI v2.0 and up
|
|
||||||
OEM_ID,
|
|
||||||
ACPI_TABLE_CREATOR,
|
|
||||||
0x20141018 // OEM revision
|
|
||||||
)
|
|
||||||
{
|
|
||||||
#include "acpi/platform.asl"
|
|
||||||
#include <cpu/intel/common/acpi/cpu.asl>
|
|
||||||
#include <southbridge/intel/common/acpi/platform.asl>
|
|
||||||
/* global NVS and variables. */
|
|
||||||
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
|
|
||||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
|
||||||
|
|
||||||
Scope (\_SB) {
|
|
||||||
Device (PCI0)
|
|
||||||
{
|
|
||||||
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
|
|
||||||
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
|
|
||||||
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
@ -1,28 +0,0 @@
|
||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or
|
|
||||||
* modify it under the terms of the GNU General Public License as
|
|
||||||
* published by the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <device/device.h>
|
|
||||||
#include <drivers/intel/gma/int15.h>
|
|
||||||
|
|
||||||
static void mainboard_enable(struct device *dev)
|
|
||||||
{
|
|
||||||
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
|
|
||||||
GMA_INT15_PANEL_FIT_DEFAULT,
|
|
||||||
GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
|
|
||||||
}
|
|
||||||
|
|
||||||
struct chip_operations mainboard_ops = {
|
|
||||||
.enable_dev = mainboard_enable,
|
|
||||||
};
|
|
||||||
|
|
@ -35,11 +35,13 @@ config VARIANT_DIR
|
||||||
string
|
string
|
||||||
default "2570p" if BOARD_HP_2570P
|
default "2570p" if BOARD_HP_2570P
|
||||||
default "2760p" if BOARD_HP_2760P
|
default "2760p" if BOARD_HP_2760P
|
||||||
|
default "8460p" if BOARD_HP_8460P
|
||||||
|
|
||||||
config MAINBOARD_PART_NUMBER
|
config MAINBOARD_PART_NUMBER
|
||||||
string
|
string
|
||||||
default "EliteBook 2570p" if BOARD_HP_2570P
|
default "EliteBook 2570p" if BOARD_HP_2570P
|
||||||
default "EliteBook 2760p" if BOARD_HP_2760P
|
default "EliteBook 2760p" if BOARD_HP_2760P
|
||||||
|
default "EliteBook 8460p" if BOARD_HP_8460P
|
||||||
|
|
||||||
config DEVICETREE
|
config DEVICETREE
|
||||||
string
|
string
|
||||||
|
|
@ -63,5 +65,6 @@ config USBDEBUG_HCD_INDEX
|
||||||
int
|
int
|
||||||
default 2 if BOARD_HP_2570P
|
default 2 if BOARD_HP_2570P
|
||||||
default 1 if BOARD_HP_2760P
|
default 1 if BOARD_HP_2760P
|
||||||
|
default 1 if BOARD_HP_8460P
|
||||||
|
|
||||||
endif
|
endif
|
||||||
|
|
|
||||||
|
|
@ -34,3 +34,17 @@ config BOARD_HP_2760P
|
||||||
select MAINBOARD_HAS_LIBGFXINIT
|
select MAINBOARD_HAS_LIBGFXINIT
|
||||||
select MAINBOARD_USES_IFD_GBE_REGION
|
select MAINBOARD_USES_IFD_GBE_REGION
|
||||||
select SOUTHBRIDGE_INTEL_BD82X6X
|
select SOUTHBRIDGE_INTEL_BD82X6X
|
||||||
|
|
||||||
|
config BOARD_HP_8460P
|
||||||
|
bool "EliteBook 8460p"
|
||||||
|
|
||||||
|
select BOARD_HP_SNB_IVB_LAPTOPS
|
||||||
|
select BOARD_ROMSIZE_KB_8192
|
||||||
|
select GFX_GMA_INTERNAL_IS_LVDS
|
||||||
|
select INTEL_INT15
|
||||||
|
select MAINBOARD_HAS_LIBGFXINIT
|
||||||
|
select MAINBOARD_HAS_LPC_TPM
|
||||||
|
select MAINBOARD_HAS_TPM1
|
||||||
|
select MAINBOARD_USES_IFD_GBE_REGION
|
||||||
|
select SOUTHBRIDGE_INTEL_BD82X6X
|
||||||
|
select SUPERIO_SMSC_LPC47N217
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue