mb/hp/8460p: Transform into variant
Tested with BUILD_TIMELESS=1, binary does not change. Change-Id: I17b6ac9ac2433b760e125a1ce708d3b422b632b5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons
Nico Huber
parent
a3580e59be
commit
5aee8262d5
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@ -1,63 +0,0 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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if BOARD_HP_8460P
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_8192
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select EC_HP_KBC1126
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select GFX_GMA_INTERNAL_IS_LVDS
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_CMOS_DEFAULT
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select HAVE_OPTION_TABLE
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select INTEL_INT15
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select MAINBOARD_HAS_LIBGFXINIT
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select MAINBOARD_HAS_LPC_TPM
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select MAINBOARD_HAS_TPM1
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select MAINBOARD_USES_IFD_GBE_REGION
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select NORTHBRIDGE_INTEL_SANDYBRIDGE
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select SERIRQ_CONTINUOUS_MODE
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select SOUTHBRIDGE_INTEL_BD82X6X
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select SUPERIO_SMSC_LPC47N217
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select SYSTEM_TYPE_LAPTOP
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select USE_NATIVE_RAMINIT
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config MAINBOARD_DIR
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string
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default "hp/8460p"
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config MAINBOARD_PART_NUMBER
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string
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default "EliteBook 8460p"
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config VGA_BIOS_FILE
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string
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default "pci8086,0116.rom"
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config VGA_BIOS_ID
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string
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default "8086,0116"
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config MAX_CPUS
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int
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default 8
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config USBDEBUG_HCD_INDEX
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int
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default 1
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endif
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@ -1,2 +0,0 @@
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config BOARD_HP_8460P
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bool "EliteBook 8460p"
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@ -1,21 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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bootblock-y += gpio.c
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romstage-y += gpio.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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bootblock-y += early_init.c
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romstage-y += early_init.c
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@ -1,16 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <ec/hp/kbc1126/acpi/ec.asl>
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@ -1,27 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Method(_WAK,1)
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{
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\_SB.PCI0.LPCB.EC0.ACPI = 1
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\_SB.PCI0.LPCB.EC0.SLPT = 0
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Return(Package(){0,0})
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}
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Method(_PTS,1)
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{
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\_SB.PCI0.LPCB.EC0.SLPT = Arg0
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}
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@ -1,16 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <drivers/pc80/pc/ps2_controller.asl>
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@ -1,27 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Vladimir Serbinenko
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <southbridge/intel/bd82x6x/nvs.h>
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void acpi_create_gnvs(global_nvs_t *gnvs)
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{
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// the lid is open by default.
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gnvs->lids = 1;
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gnvs->tcrt = 100;
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gnvs->tpsv = 90;
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}
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@ -1,6 +0,0 @@
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boot_option=Fallback
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debug_level=Debug
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power_on_after_fail=Disable
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nmi=Enable
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volume=0x3
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sata_mode=AHCI
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@ -1,116 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2008 coresystems GmbH
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## Copyright (C) 2014 Vladimir Serbinenko
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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# -----------------------------------------------------------------
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entries
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# -----------------------------------------------------------------
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# Status Register A
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# -----------------------------------------------------------------
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# Status Register B
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# -----------------------------------------------------------------
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# Status Register C
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#96 4 r 0 status_c_rsvd
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#100 1 r 0 uf_flag
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#101 1 r 0 af_flag
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#102 1 r 0 pf_flag
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#103 1 r 0 irqf_flag
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# -----------------------------------------------------------------
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# Status Register D
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#104 7 r 0 status_d_rsvd
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#111 1 r 0 valid_cmos_ram
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# -----------------------------------------------------------------
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# Diagnostic Status Register
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#112 8 r 0 diag_rsvd1
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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#120 264 r 0 unused
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 4 boot_option
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388 4 h 0 reboot_counter
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#390 2 r 0 unused?
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# -----------------------------------------------------------------
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# coreboot config options: console
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#392 3 r 0 unused
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395 4 e 6 debug_level
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#399 1 r 0 unused
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#400 8 r 0 reserved for century byte
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# coreboot config options: southbridge
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408 1 e 1 nmi
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409 2 e 7 power_on_after_fail
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421 1 e 9 sata_mode
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# coreboot config options: cpu
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#424 8 r 0 unused
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# coreboot config options: northbridge
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432 3 e 11 gfx_uma_size
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#435 5 r 0 unused
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440 8 h 0 volume
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# SandyBridge MRC Scrambler Seed values
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896 32 r 0 mrc_scrambler_seed
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928 32 r 0 mrc_scrambler_seed_s3
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960 16 r 0 mrc_scrambler_seed_chk
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# coreboot config options: check sums
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984 16 h 0 check_sum
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# -----------------------------------------------------------------
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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6 0 Emergency
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6 1 Alert
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6 2 Critical
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6 3 Error
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6 4 Warning
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6 5 Notice
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6 6 Info
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6 7 Debug
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6 8 Spew
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7 0 Disable
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7 1 Enable
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7 2 Keep
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9 0 AHCI
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9 1 Compatible
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11 0 32M
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11 1 64M
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11 2 96M
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11 3 128M
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11 4 160M
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11 5 192M
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11 6 224M
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# -----------------------------------------------------------------
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checksums
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checksum 392 447 984
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@ -1,44 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
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#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
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#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
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#include <arch/acpi.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x02, // DSDT revision: ACPI v2.0 and up
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20141018 // OEM revision
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)
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{
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#include "acpi/platform.asl"
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#include <cpu/intel/common/acpi/cpu.asl>
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#include <southbridge/intel/common/acpi/platform.asl>
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/* global NVS and variables. */
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#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
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#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
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#include <southbridge/intel/bd82x6x/acpi/pch.asl>
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}
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}
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}
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@ -1,28 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/device.h>
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#include <drivers/intel/gma/int15.h>
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static void mainboard_enable(struct device *dev)
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{
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install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
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GMA_INT15_PANEL_FIT_DEFAULT,
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GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
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}
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struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
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};
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@ -35,11 +35,13 @@ config VARIANT_DIR
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string
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default "2570p" if BOARD_HP_2570P
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default "2760p" if BOARD_HP_2760P
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default "8460p" if BOARD_HP_8460P
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config MAINBOARD_PART_NUMBER
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string
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default "EliteBook 2570p" if BOARD_HP_2570P
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default "EliteBook 2760p" if BOARD_HP_2760P
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default "EliteBook 8460p" if BOARD_HP_8460P
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config DEVICETREE
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string
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@ -63,5 +65,6 @@ config USBDEBUG_HCD_INDEX
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int
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default 2 if BOARD_HP_2570P
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default 1 if BOARD_HP_2760P
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default 1 if BOARD_HP_8460P
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endif
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@ -34,3 +34,17 @@ config BOARD_HP_2760P
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select MAINBOARD_HAS_LIBGFXINIT
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select MAINBOARD_USES_IFD_GBE_REGION
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select SOUTHBRIDGE_INTEL_BD82X6X
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config BOARD_HP_8460P
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bool "EliteBook 8460p"
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select BOARD_HP_SNB_IVB_LAPTOPS
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select BOARD_ROMSIZE_KB_8192
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select GFX_GMA_INTERNAL_IS_LVDS
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select INTEL_INT15
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select MAINBOARD_HAS_LIBGFXINIT
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select MAINBOARD_HAS_LPC_TPM
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select MAINBOARD_HAS_TPM1
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select MAINBOARD_USES_IFD_GBE_REGION
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select SOUTHBRIDGE_INTEL_BD82X6X
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select SUPERIO_SMSC_LPC47N217
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Reference in New Issue