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nb/intel/sandybridge/raminit: Fix SMBIOS 17 bus width 

The bus width has to be encoded where the lower 3 bits are the bus width
in multiple of 8 and the following two bits give the error checking
bits in multiple of 8.
Hardcode to 64 bit as done on haswell.
TODO: Make it dynamic once there's ECC support.

Change-Id: I3b83a098205455b1c820d0436c6984938f261466
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Patrick Rudolph 2017-10-31 11:53:13 +01:00 committed by Felix Held
parent 652c491917
commit 5af2deae92
1 changed files with 1 additions and 1 deletions
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src/northbridge/intel/sandybridge/raminit.c
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@ -113,7 +113,7 @@ static void fill_smbios17(ramctr_timing *ctrl)
info->dimm[channel][slot].part_number, 16); info->dimm[channel][slot].part_number, 16);
dimm->mod_id = info->dimm[channel][slot].manufacturer_id; dimm->mod_id = info->dimm[channel][slot].manufacturer_id;
dimm->mod_type = info->dimm[channel][slot].dimm_type; dimm->mod_type = info->dimm[channel][slot].dimm_type;
dimm->bus_width = info->dimm[channel][slot].width; dimm->bus_width = MEMORY_BUS_WIDTH_64; // non-ECC only
mem_info->dimm_cnt++; mem_info->dimm_cnt++;
} }
} }