GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/amd/common/block/psp: add psp_efs.c to build for both PSP GEN1&2 

The PSP EFS code to get the SPI mode and speed from the amdfw part of
the firmware image also works for Stoneyridge which is the one SoC that
selects SOC_AMD_COMMON_BLOCK_PSP_GEN1. Also amdblocks/psp_efs.h already
handles the SOC_AMD_STONEYRIDGE case.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibddd3f9237e561d9f0f6b4ad70f59cce1f956986
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Felix Held 2021-12-08 00:12:06 +01:00
parent 2a8de6dafb
commit 5af890d666
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/soc/amd/common/block/psp/Makefile.inc
View File

@ -5,6 +5,9 @@ ramstage-y += psp.c
smm-y += psp.c smm-y += psp.c
smm-y += psp_smm.c smm-y += psp_smm.c
bootblock-y += psp_efs.c
verstage-y += psp_efs.c
endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP
ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN1),y) ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN1),y)
@ -22,7 +25,4 @@ ramstage-y += psp_gen2.c
smm-y += psp_gen2.c smm-y += psp_gen2.c
smm-y += psp_smm_gen2.c smm-y += psp_smm_gen2.c
bootblock-y += psp_efs.c
verstage-y += psp_efs.c
endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2 endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2