stoneyridge: Enable IO CF9 in bootblock

If IO CF9 is not enabled, hard_reset() won't do anything in bootblock or
verstage.

BUG=b:110817463
TEST=built on grunt and made sure that hard_reset() reboots.

Change-Id: I5f091077a17db3dfe5b8e8367163312db6828360
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27267
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Raul E Rangel 2018-06-28 16:31:45 -06:00 committed by Patrick Georgi
parent 6756c16e82
commit 5b05823388
2 changed files with 10 additions and 0 deletions

View File

@ -32,6 +32,8 @@
#define PSP_MAILBOX_BAR_EN 0x10
/* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */
#define PM_DECODE_EN 0x00
#define CF9_IO_EN BIT(1)
#define PM_ISA_CONTROL 0x04
#define MMIO_EN BIT(1)
#define PM_PCI_CTRL 0x08

View File

@ -368,6 +368,13 @@ void sb_acpi_mmio_decode(void)
outb(byte, PM_DATA);
}
static void sb_enable_cf9_io(void)
{
uint32_t reg = pm_read32(PM_DECODE_EN);
pm_write32(PM_DECODE_EN, reg | CF9_IO_EN);
}
void sb_clk_output_48Mhz(void)
{
u32 ctrl;
@ -542,6 +549,7 @@ void bootblock_fch_early_init(void)
sb_spibase();
sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */
sb_acpi_mmio_decode();
sb_enable_cf9_io();
enable_aoac_devices();
}