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soc/xeon_sp: add configs to use common/gpio diver 

Allow the use of the common/gpio driver to create Lewisburg PCH pad
configurations for server motherboards with Skylake-SP processors.

This patch should only be applied after adding Lewisburg PCH definitions
to the soc/intel/xeon_sp code [1].

[1] https://review.coreboot.org/c/coreboot/+/39425

Change-Id: I4a8e83cad0729bbbb50ba5a2b336f6cf7c1eca13
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Maxim Polyakov 2020-03-22 14:57:36 +03:00 committed by Andrey Petrov
parent ce2399a446
commit 5b06ffea56
1 changed files with 4 additions and 0 deletions
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4
src/soc/intel/xeon_sp/Kconfig
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@ -61,6 +61,10 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_RTC
select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_SPI
select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_FAST_SPI
select SOC_INTEL_COMMON_BLOCK_GPIO
select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS
select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_PCR
select TSC_MONOTONIC_TIMER select TSC_MONOTONIC_TIMER
select UDELAY_TSC select UDELAY_TSC