libpayload EHCI: Add memory barrier to EHCI driver
EHCI driver accesses mmio space using regular struct pointers. In order to avoid any CPU re-ordering, memory barrier is required in async_set_schedule, especially for arm64. Without the memory barrier, there seems to be re-ordering taking place which leads to USB errors with some flash drives as well as transfer errors in netboot. BUG=chrome-os-partner:31533 BRANCH=None TEST=With the memory barrier introduced, netboot for ryu completes transfer without any error and finishes within 6-7 seconds. Change-Id: Ib6d29dc79fd5722c27284478e8da316929e86bff Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 561bdd746c4d4446ce0a6d21337d354625d85ddc Original-Change-Id: Ic05d47422312a1cddbebe3180f4f159853604440 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/213917 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8732 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -30,6 +30,7 @@
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//#define USB_DEBUG
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#include <libpayload.h>
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#include <arch/barrier.h>
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#include <arch/cache.h>
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#include "ehci.h"
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#include "ehci_private.h"
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@ -317,6 +318,14 @@ static int wait_for_tds(qtd_t *head)
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static int ehci_set_async_schedule(ehci_t *ehcic, int enable)
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{
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/* Memory barrier to ensure that all memory accesses before we set the
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* async schedule are complete. It was observed especially in the case of
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* arm64, that netboot and usb stuff resulted in lots of errors possibly
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* due to CPU reordering. Hence, enforcing strict CPU ordering.
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*/
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mb();
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/* Set async schedule status. */
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if (enable)
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ehcic->operation->usbcmd |= HC_OP_ASYNC_SCHED_EN;
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