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intel/kunimitsu: Coreboot GPIO changes for FAB 4. 

This patch adds GPIO mappings for PCH_BUZZER, AUDIO_DB_ID,
AUDIO_IRQ and BOOT_BEEP.

BUG=chrome-os-partner:47513
BRANCH=none
TEST=Built for kunimitsu but not verified on Fab 4.

Change-Id: I0172df3aa2a5c4bfc24422aa0bfb7e5f677d37c9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ba66bef6d402a1040f0f13bc828de400bc6371b7
Original-Change-Id: I1f2ed8fc283883a523a77e07de14ed90057b719b
Original-Signed-off-by: Saurabh Satija <saurabh.satija@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311806
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/12600
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Saurabh Satija 2015-10-26 15:00:46 -07:00 committed by Patrick Georgi
parent 7a2963b86c
commit 5b242f6307
1 changed files with 5 additions and 5 deletions
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10
src/mainboard/intel/kunimitsu/gpio.h
View File

@ -60,7 +60,7 @@ static const struct pad_config gpio_table[] = {
/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), /* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
/* PIRQA# */ /* GPP_A7 */ /* SD_CD_WAKE */ PAD_CFG_GPI(GPP_A7, 20K_PU, DEEP),
/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
/* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
/* PCH_LPC_CLK */ /* GPP_A10 */ /* PCH_LPC_CLK */ /* GPP_A10 */
@ -91,7 +91,7 @@ static const struct pad_config gpio_table[] = {
/* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
/* GPP_B_14_SPKR */ PAD_CFG_GPI(GPP_B14, NONE, DEEP), /* PCH_BUZZER */ PAD_CFG_GPI(GPP_B14, NONE, DEEP),
/* GSPI0_CS# */ /* GPP_B15 */ /* GSPI0_CS# */ /* GPP_B15 */
/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), /* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES),
/* SSD_PCIE_WAKE */ PAD_CFG_GPI(GPP_B17, NONE, DEEP), /* SSD_PCIE_WAKE */ PAD_CFG_GPI(GPP_B17, NONE, DEEP),
@ -152,7 +152,7 @@ static const struct pad_config gpio_table[] = {
/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP), /* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP),
/* SATAXPCIE1 */ /* GPP_E1 */ /* SATAXPCIE1 */ /* GPP_E1 */
/* SSD_PEDET */ PAD_CFG_GPI(GPP_E2, NONE, DEEP), /* SSD_PEDET */ PAD_CFG_GPI(GPP_E2, NONE, DEEP),
/* CPU_GP0 */ /* GPP_E3 */ /* AUDIO_DB_ID */ PAD_CFG_GPI(GPP_E3, NONE, DEEP),
/* SSD_SATA_DEVSLP */ PAD_CFG_GPO(GPP_E4, 0, DEEP), /* SSD_SATA_DEVSLP */ PAD_CFG_GPO(GPP_E4, 0, DEEP),
/* SATA_DEVSLP1 */ /* GPP_E5 */ /* SATA_DEVSLP1 */ /* GPP_E5 */
/* SATA_DEVSLP2 */ /* GPP_E6 */ /* SATA_DEVSLP2 */ /* GPP_E6 */
@ -184,7 +184,7 @@ static const struct pad_config gpio_table[] = {
/* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
/* I2C4_SDA */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* I2C4_SDA */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), /* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP),
/* I2C5_SCL */ /* GPP_F11 */ /* AUDIO_IRQ */ PAD_CFG_GPI_ACPI_SCI(GPP_F11, NONE, DEEP, YES),
/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
@ -196,7 +196,7 @@ static const struct pad_config gpio_table[] = {
/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
/* GPP_F23 */ /* BOOT_BEEP */ PAD_CFG_GPO(GPP_F23, 1, DEEP),
/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), /* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), /* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), /* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),