fixup
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1596 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -14,12 +14,6 @@ uses CONFIG_BRIQ_7400
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default PCIC0_CFGADDR=0xff508000
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default PCIC0_CFGDATA=0xff508010
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##
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## Set IDE control registers
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##
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default PNP_CFGADDR=0x1f0
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default PNP_CFGDATA=0x1f1
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##
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## Set UART base address
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##
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@ -28,8 +22,13 @@ default TTYS0_BASE=0x3f8
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##
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## Early board initialization, called from ppc_main()
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##
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initobject init.c
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driver pci_bridge.c
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initobject init.o
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initobject clock.o
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##
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## Stage 2 timer support
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##
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object clock.o
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arch ppc end
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@ -43,6 +42,7 @@ end
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##
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## Include the secondary Configuration files
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##
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northbridge ibm/cpc710 end
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southbridge winbond/w83c553 end
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##
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