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fixup 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1596 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Greg Watson 2004-06-03 16:55:24 +00:00
parent f78ba9dfa6
commit 5b2565a6df
1 changed files with 8 additions and 8 deletions
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16
src/mainboard/totalimpact/briq/Config.lb
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@ -14,12 +14,6 @@ uses CONFIG_BRIQ_7400
default PCIC0_CFGADDR=0xff508000 default PCIC0_CFGADDR=0xff508000
default PCIC0_CFGDATA=0xff508010 default PCIC0_CFGDATA=0xff508010
##
## Set IDE control registers
##
default PNP_CFGADDR=0x1f0
default PNP_CFGDATA=0x1f1
## ##
## Set UART base address ## Set UART base address
## ##
@ -28,8 +22,13 @@ default TTYS0_BASE=0x3f8
## ##
## Early board initialization, called from ppc_main() ## Early board initialization, called from ppc_main()
## ##
initobject init.c initobject init.o
driver pci_bridge.c initobject clock.o
##
## Stage 2 timer support
##
object clock.o
arch ppc end arch ppc end
@ -43,6 +42,7 @@ end
## ##
## Include the secondary Configuration files ## Include the secondary Configuration files
## ##
northbridge ibm/cpc710 end
southbridge winbond/w83c553 end southbridge winbond/w83c553 end
## ##