vendorcode/intel: Update FSP Header files per v2.0.0
Update FSP header files to match GLK FSP Reference Code Release v2.0.0 Change-Id: I93d95e1977a4e31981e8b91882059611d91f78a5 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/25247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Srinidhi N Kaushik
Furquan Shaikh
parent
4183260304
commit
5b2a4b4087
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@ -1,6 +1,6 @@
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/** @file
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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@ -52,6 +52,9 @@ are permitted provided that the following conditions are met:
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#define MAX_SPD_SAVE 29
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#endif
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#define MRC_DDR_TYPE_LPDDR4 6
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#define MRC_DDR_TYPE_DDR4 7
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//
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// MRC version description.
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//
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@ -805,11 +808,9 @@ typedef struct {
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**/
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UINT32 OemLoadingBase;
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/** Offset 0x0120 - OEM File Name to Load
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Specify a file name to load from CSE file system after memory is available. Empty
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indicates no file needs to be loaded.
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/** Offset 0x0120
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**/
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UINT8 OemFileName[16];
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UINT8 Reserved[16];
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/** Offset 0x0130
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**/
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@ -962,37 +963,41 @@ typedef struct {
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**/
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VOID* VariableNvsBufferPtr;
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/** Offset 0x0164
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/** Offset 0x0164 - PERST pin for RootPort 0
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Address for PERST pin for Rootport 0. For Intel RVP, address of N_GPIO_105. 0x00C507D0(Default).
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**/
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UINT32 RootPort0Perst;
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/** Offset 0x0168 - PERST pin for RootPort 1
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Address for PERST pin for Rootport 1. For Intel RVP, address of A_GPIO_163. 0x00C90670(Default).
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**/
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UINT32 RootPort1Perst;
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/** Offset 0x016C - PERST pin for RootPort 2
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Address for PERST pin for Rootport 2. For Intel RVP, address of N_GPIO_137. 0x00C509D0(Default).
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**/
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UINT32 RootPort2Perst;
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/** Offset 0x0170 - PERST pin for RootPort 3
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Address for PERST pin for Rootport 3.
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**/
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UINT32 RootPort3Perst;
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/** Offset 0x0174 - PERST pin for RootPort 4
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Address for PERST pin for Rootport 4. For Intel RVP, address of SCC_GPIO_210. 0x00C806D0(Default).
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**/
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UINT32 RootPort4Perst;
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/** Offset 0x0178 - PERST pin for RootPort 5
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Address for PERST pin for Rootport 5.
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**/
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UINT32 RootPort5Perst;
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/** Offset 0x017C
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**/
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UINT8 ReservedFspmUpd[4];
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} FSP_M_CONFIG;
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/** Fsp M Test Configuration
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**/
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typedef struct {
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/** Offset 0x0168
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**/
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UINT32 Signature;
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/** Offset 0x016C
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**/
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UINT8 ReservedFspmTestUpd[20];
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} FSP_M_TEST_CONFIG;
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/** Fsp M Restricted Configuration
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**/
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typedef struct {
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/** Offset 0x0180
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**/
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UINT32 Signature;
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/** Offset 0x0184
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**/
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UINT8 ReservedFspmRestrictedUpd[124];
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} FSP_M_RESTRICTED_CONFIG;
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/** Fsp M UPD Configuration
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**/
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typedef struct {
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@ -1009,17 +1014,9 @@ typedef struct {
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**/
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FSP_M_CONFIG FspmConfig;
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/** Offset 0x0168
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**/
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FSP_M_TEST_CONFIG FspmTestConfig;
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/** Offset 0x0180
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**/
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FSP_M_RESTRICTED_CONFIG FspmRestrictedConfig;
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/** Offset 0x0200
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**/
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UINT8 UnusedUpdSpace1[6];
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UINT8 UnusedUpdSpace1[134];
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/** Offset 0x0206
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**/
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@ -1,6 +1,6 @@
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/** @file
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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@ -1672,74 +1672,40 @@ typedef struct {
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**/
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UINT16 HgSubSystemId;
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/** Offset 0x0388
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/** Offset 0x0388 - USB Per Port HS Preemphasis Bias
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USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-40.5mV, 010b-60.5mV, 011b-102mV,
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100b-102mV, 101b-142mV, 110b-162.5mV, 111b-202.5mV. One byte for each port.
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**/
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UINT8 ReservedFspsUpd[8];
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UINT8 Usb2AfePetxiset[8];
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/** Offset 0x0390 - USB Per Port HS Transmitter Bias
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USB Per Port HS Transmitter Bias. 000b-0mV, 001b-40.5mV, 010b-60.5mV, 011b-102mV,
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100b-102mV, 101b-142mV, 110b-162.5mV, 111b-202.5mV. One byte for each port.
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**/
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UINT8 Usb2AfeTxiset[8];
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/** Offset 0x0398 - USB Per Port HS Transmitter Emphasis
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USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON,
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10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.
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**/
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UINT8 Usb2AfePredeemp[8];
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/** Offset 0x03A0 - USB Per Port Half Bit Pre-emphasis
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USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis.
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One byte for each port.
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**/
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UINT8 Usb2AfePehalfbit[8];
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/** Offset 0x03A8 - Intel Processor Trace output Scheme method
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Intel Processor Trace output Scheme method 0:Single Range Output (Default) 1. ToPA Output
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**/
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UINT8 ProcessorTraceOutputScheme;
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/** Offset 0x03A9
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**/
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UINT8 ReservedFspsUpd[7];
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} FSP_S_CONFIG;
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/** Fsp S Test Configuration
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**/
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typedef struct {
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/** Offset 0x0390
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**/
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UINT32 Signature;
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/** Offset 0x0394
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**/
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UINT8 ReservedFspsTestUpd[12];
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} FSP_S_TEST_CONFIG;
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/** Fsp S Restricted Configuration
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**/
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typedef struct {
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/** Offset 0x03A0
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**/
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UINT32 Signature;
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/** Offset 0x03A4 - Selective enable SGX
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Selective enable SGX. 0xFFFF(Default).
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**/
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UINT16 SelectiveEnableSgx;
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/** Offset 0x03A6 - SGX debug mode
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Select SGX mode. 0:Disable(default), 1:Enable
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0:Disable(default), 1:Enable
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**/
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UINT8 SgxDebugMode;
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/** Offset 0x03A7 - SGX Launch Control Policy Mode
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Select Launch Control Policy Mode. 0:Intel - Default, 1:Per-boot Select mode(default)
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0:Intel locked , 1:Unlocked mode(default) , 2: Locked mode
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**/
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UINT8 SgxLcp;
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/** Offset 0x03A8 - LE KeyHash0
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LE KeyHash0. 0x0(Default).
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**/
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UINT64 SgxLePubKeyHash0;
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/** Offset 0x03B0 - LE KeyHash1
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LE KeyHash1. 0x0(Default).
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**/
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UINT64 SgxLePubKeyHash1;
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/** Offset 0x03B8 - LE KeyHash2
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LE KeyHash2. 0x0(Default).
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**/
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UINT64 SgxLePubKeyHash2;
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/** Offset 0x03C0 - LE KeyHash3
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LE KeyHash3. 0x0(Default).
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**/
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UINT64 SgxLePubKeyHash3;
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/** Offset 0x03C8
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**/
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UINT8 ReservedFspsRestrictedUpd[8];
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} FSP_S_RESTRICTED_CONFIG;
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/** Fsp S UPD Configuration
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**/
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typedef struct {
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@ -1752,19 +1718,11 @@ typedef struct {
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**/
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FSP_S_CONFIG FspsConfig;
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/** Offset 0x0390
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/** Offset 0x03B0
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**/
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FSP_S_TEST_CONFIG FspsTestConfig;
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UINT8 UnusedUpdSpace7[78];
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/** Offset 0x03A0
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**/
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FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig;
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/** Offset 0x03D0
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**/
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UINT8 UnusedUpdSpace7[6];
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/** Offset 0x03D6
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/** Offset 0x03FE
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**/
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UINT16 UpdTerminator;
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} FSPS_UPD;
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