diff --git a/src/southbridge/intel/i82371eb/i82371eb_ide.c b/src/southbridge/intel/i82371eb/i82371eb_ide.c index f1b618fa71..f72bcb63c6 100644 --- a/src/southbridge/intel/i82371eb/i82371eb_ide.c +++ b/src/southbridge/intel/i82371eb/i82371eb_ide.c @@ -48,14 +48,14 @@ static void ide_init_enable(struct device *dev) reg16 = pci_read_config16(dev, IDETIM_PRI); reg16 = ONOFF(conf->ide0_enable, reg16, IDE_DECODE_ENABLE); pci_write_config16(dev, IDETIM_PRI, reg16); - printk(BIOS_DEBUG, "IDE: %s: %s\n", "Primary IDE interface", + printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Primary", conf->ide0_enable ? "on" : "off"); /* Enable/disable the secondary IDE interface. */ reg16 = pci_read_config16(dev, IDETIM_SEC); reg16 = ONOFF(conf->ide1_enable, reg16, IDE_DECODE_ENABLE); pci_write_config16(dev, IDETIM_SEC, reg16); - printk(BIOS_DEBUG, "IDE: %s: %s\n", "Secondary IDE interface", + printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Secondary", conf->ide1_enable ? "on" : "off"); /* Enable access to the legacy IDE ports (both primary and secondary), diff --git a/src/southbridge/intel/i82801ax/i82801ax_ide.c b/src/southbridge/intel/i82801ax/i82801ax_ide.c index 98bc542d07..c5bd2882b4 100644 --- a/src/southbridge/intel/i82801ax/i82801ax_ide.c +++ b/src/southbridge/intel/i82801ax/i82801ax_ide.c @@ -38,7 +38,7 @@ static void ide_init(struct device *dev) reg16 &= ~IDE_DECODE_ENABLE; if (!conf || conf->ide0_enable) reg16 |= IDE_DECODE_ENABLE; - printk(BIOS_DEBUG, "IDE: %s: %s\n", "Primary IDE interface", + printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Primary", conf->ide0_enable ? "on" : "off"); pci_write_config16(dev, IDE_TIM_PRI, reg16); @@ -46,7 +46,7 @@ static void ide_init(struct device *dev) reg16 &= ~IDE_DECODE_ENABLE; if (!conf || conf->ide1_enable) reg16 |= IDE_DECODE_ENABLE; - printk(BIOS_DEBUG, "IDE: %s: %s\n", "Primary IDE interface", + printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Secondary", conf->ide0_enable ? "on" : "off"); pci_write_config16(dev, IDE_TIM_SEC, reg16); }