From 5b334b88a635e46d47ce3f3b703d2470d6e8514c Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 30 Nov 2021 18:34:32 +0100 Subject: [PATCH] x86_64 assembly: Don't touch %gs With CPU_INFO_V2 enabled %gs holds the pointer to the cpu_info struct, so don't clobber it. Backup and restore %gs where possible. Fixes a crash in MPinit seen after calling FSP-S. Change-Id: If9fc999b34530de5d8b6ad27b9af25fc552e9420 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/59764 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/cpu/x86/64bit/exit32.inc | 1 - src/cpu/x86/64bit/mode_switch.S | 14 ++++++++++---- src/security/intel/txt/getsec_enteraccs.S | 6 ++++++ 3 files changed, 16 insertions(+), 5 deletions(-) diff --git a/src/cpu/x86/64bit/exit32.inc b/src/cpu/x86/64bit/exit32.inc index 4d1149ee6c..3ac86a9df1 100644 --- a/src/cpu/x86/64bit/exit32.inc +++ b/src/cpu/x86/64bit/exit32.inc @@ -68,7 +68,6 @@ __longmode_compatibility: movl %eax, %es movl %eax, %ss movl %eax, %fs - movl %eax, %gs /* Disable paging. */ movl %cr0, %eax diff --git a/src/cpu/x86/64bit/mode_switch.S b/src/cpu/x86/64bit/mode_switch.S index eea104bcf3..c27f540ba3 100644 --- a/src/cpu/x86/64bit/mode_switch.S +++ b/src/cpu/x86/64bit/mode_switch.S @@ -15,6 +15,10 @@ protected_mode_call_narg: push %r14 push %r15 + /* Backup gs to stack */ + movl %gs, %eax + push %rax + /* Arguments to stack */ push %rdi push %rsi @@ -23,9 +27,9 @@ protected_mode_call_narg: #include - movl -48(%ebp), %eax /* Argument count */ - movl -64(%ebp), %edx /* Argument 0 */ - movl -72(%ebp), %ecx /* Argument 1 */ + movl -56(%ebp), %eax /* Argument count */ + movl -72(%ebp), %edx /* Argument 0 */ + movl -80(%ebp), %ecx /* Argument 1 */ /* Align the stack */ andl $0xFFFFFFF0, %esp @@ -46,7 +50,7 @@ protected_mode_call_narg: pushl %edx /* Argument 0 */ 1: - movl -56(%ebp), %ebx /* Function to call */ + movl -64(%ebp), %ebx /* Function to call */ call *%ebx movl %eax, %ebx @@ -57,6 +61,8 @@ protected_mode_call_narg: movl %ebx, %eax /* Restore registers */ + mov -48(%rbp), %rbx + movl %ebx, %gs mov -40(%rbp), %r15 mov -32(%rbp), %r14 mov -24(%rbp), %r13 diff --git a/src/security/intel/txt/getsec_enteraccs.S b/src/security/intel/txt/getsec_enteraccs.S index 09f9f389e6..cbb24b6511 100644 --- a/src/security/intel/txt/getsec_enteraccs.S +++ b/src/security/intel/txt/getsec_enteraccs.S @@ -227,6 +227,10 @@ cond_clear_var_mtrrs: movd %esp, %xmm0 movd %ebp, %xmm1 + /* Backup %gs used by CPU_INFO_V2 */ + movl %gs, %eax + movd %eax, %xmm2 + /* * Get function arguments. * It's important to pass the exact ACM size as it's used by getsec to verify @@ -261,6 +265,8 @@ cond_clear_var_mtrrs: movl %eax, %es movl %eax, %ss movl %eax, %fs + /* Restore %gs used by CPU_INFO_V2 */ + movd %xmm2, %eax movl %eax, %gs /* Disable cache */